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Cortex-M3 Processor Registers
2.7.4.26 CPUID Register (Offset = D00h) [reset = 412FC231h]
CPUID is shown in
and described in
.
CPUID Base This register determines the ID number of the processor core, the version number of the
processor core and the implementation details of the processor core.
processor core and the implementation details of the processor core.
Figure 2-96. CPUID Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
IMPLEMENTER
VARIANT
CONSTANT
R-41h
R-2h
R-Fh
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PARTNO
REVISION
R-C23h
R-1h
Table 2-122. CPUID Register Field Descriptions
Bit
Field
Type
Reset
Description
31-24
IMPLEMENTER
R
41h
Implementor code.
23-20
VARIANT
R
2h
Implementation defined variant number.
19-16
CONSTANT
R
Fh
Reads as 0xF
15-4
PARTNO
R
C23h
Number of processor within family.
3-0
REVISION
R
1h
Implementation defined revision number.
166
SWCU117A – February 2015 – Revised March 2015
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