Техническая Спецификация для Texas Instruments The ADC12DC105 is a dual 12-Bit, 105 Msps A/D Converter ADC12DC105LFEB/NOPB ADC12DC105LFEB/NOPB
Модели
ADC12DC105LFEB/NOPB
AGND
V
A
AGND
V
A
AGND
V
A
V
A
V
A
V
A
V
A
AGND
AGND
V
A
AGND
SNAS469A – SEPTEMBER 2008 – REVISED OCTOBER 2008
PIN DESCRIPTIONS
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
3
V
IN
A+
13
V
IN
B+
Differential analog input pins. The differential full-scale input signal
level is 2V
level is 2V
P-P
with each input pin signal centered on a common mode
2
V
IN
A-
voltage, V
CM
.
14
V
IN
B-
(1)
5
V
RP
A
11
V
RP
B
7
V
CMO
A
9
V
CMO
B
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very close to
the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor
should be placed between V
(equivalent series inductance) 0.1 µF capacitor placed very close to
the pin to minimize stray inductance. An 0201 size 0.1 µF capacitor
should be placed between V
RP
and V
RN
as close to the pins as
possible, and a 1 µF capacitor should be placed in parallel.
V
V
RP
and V
RN
should not be loaded. V
CMO
may be loaded to 1mA for
6
V
RN
A
use as a temperature stable 1.5V reference.
10
V
RN
B
It is recommended to use V
CMO
to provide the common mode
voltage, V
CM
, for the differential analog inputs.
(2)
Reference Voltage. This device provides an internally developed
1.2V reference. When using the internal reference, V
1.2V reference. When using the internal reference, V
REF
should be
decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series
59
V
REF
inductance (ESL) capacitor.
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current when the
internal reference is used.
This pin may be driven with an external 1.2V reference voltage.
This pin should not be used to source or sink current when the
internal reference is used.
(3)
DIGITAL I/O
This is a four-state pin controlling the input clock mode and output
data format.
OF/DCS = V
data format.
OF/DCS = V
A
, output data format is 2's complement without duty
cycle stabilization applied to the input clock.
OF/DCS = AGND, output data format is offset binary, without duty
OF/DCS = AGND, output data format is offset binary, without duty
19
OF/DCS
cycle stabilization applied to the input clock.
OF/DCS = (2/3)*V
OF/DCS = (2/3)*V
A
, output data is 2's complement with duty cycle
stabilization applied to the input clock.
OF/DCS = (1/3)*V
OF/DCS = (1/3)*V
A
, output data is offset binary with duty cycle
(4)
stabilization applied to the input clock.
The clock input pin.
18
CLK
The analog inputs are sampled on the rising edge of the clock input.
This is a two-state input controlling Power Down.
57
PD_A
PD = V
A
, Power Down is enabled and power dissipation is reduced.
20
PD_B
PD = AGND, Normal operation.
(5)
Copyright © 2008, Texas Instruments Incorporated
3
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