Техническая Спецификация для Texas Instruments DS90C187 Evaluation Module C187EVK01/NOPB C187EVK01/NOPB

SNLU102-May 2012 

                                                                                                                        C187EVK01 User’s Guide  

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This section describes the jumpers and connectors on the EVK as well and how to properly connect, set up 
and use the C187EVK01.  
 
 

JP1 – MODE1 is to be used in combination with JP2 (MODE0) to configure the DS90C187. Refer to Table 2. 
 
JP2 – MODE0 is to be used in combination with JP1 (MODE1) to configure the DS90C187. Refer to Table 2. 
 

0 

0 

SISO – Single Pixel In Single Pixel Out 

0 

1 

SIDO – Single Pixel In Dual Pixel Out 

1 

0 

DIDO – Dual Pixel In Dual Pixel Out 

1 1 

 
JP3 – RFB is the jumper that selects the clock edge that the input LVCMOS data will be sampled on. If RFB 
is logic HIGH, the input data is latched on the RISING EDGE of the pixel clock. If RFB is set to logic LOW, 
the input data is latched on the FALLING EDGE of the pixel clock. 
 

 

 

JP4 – PDB is the jumper used to enable the Serializer. Power Down Bar (PDB) set to logic HIGH enables the 
device, while connecting this jumper to logic LOW will disable the device.  
 
JP5 – 18B is the jumper used to enable a power saving mode for 18-bit color applications. When this jumper 
is set to logic LOW, all data inputs will be sampled, serialized and driven out through the LVDS drivers to 
support 24-bit color applications or 28-bit generic data buses. If this jumper is set to logic HIGH, the device 
will enter a power saving mode that will power down the circuitry that feeds the 4

th

 data LVDS driver and also 

the 8th data LVDS driver for dual pixel output configurations. In dual pixel outputs configurations the 4

th

 data 

LVDS driver, OA_3+/-, and 8

th

 data LVDS driver, OB_3+/- will be TRI-STATE®. 

 
JP6 – VODSEL is the jumper that controls the differential output voltage. When VODSEL is set to logic 
HIGH, the output launch amplitude of the LVDS drivers will be set to have a larger output swing. If this jumper 
is set to logic LOW, then the LVDS drivers will be configured to have a power saving smaller output swing. 
 
JP7 – LVDSSWAP is reserved for future use and should be tied LOW.