Техническая Спецификация для Texas Instruments DRV8836 Evaluation Module DRV8836EVM DRV8836EVM
Модели
DRV8836EVM
Jumpers and Controls
3
Jumpers and Controls
3.1
JP1 – VCC (DRV8835) or nSLEEP (DRV8836)
For DRV8835EVM, the JP1 jumper MUST be installed for proper operation.
For DRV8836EVM, installing the JP1 jumper will place the device in an active state. Removing the jumper
will pull the input to GND through an internal pull-down resistor and the device will be in an inactive or
sleep state.
will pull the input to GND through an internal pull-down resistor and the device will be in an inactive or
sleep state.
3.2
JP2 – MODE Select
JP2 is used to select the input signal control mode. Installing the JP2 jumper will pull the MODE pin high
and the device will be in a “PHASE/ENABLE” mode. Removing the jumper on JP2 will put the device in an
“IN/IN” mode. Please refer to the datasheet for a description of these different modes.
and the device will be in a “PHASE/ENABLE” mode. Removing the jumper on JP2 will put the device in an
“IN/IN” mode. Please refer to the datasheet for a description of these different modes.
3.3
JP3, JP4, JP5, and JP7 – Source Select Jumpers
Installing jumpers across position 1-2 on all 4 headers will allow control of the device through the J2
header using an external microprocessor of other logic. Installing jumpers across positions 2-3, will allow
the switches (S1-S4) to control the inputs with either a “high” or “low” depending on the switch location.
header using an external microprocessor of other logic. Installing jumpers across positions 2-3, will allow
the switches (S1-S4) to control the inputs with either a “high” or “low” depending on the switch location.
3.4
JP6 – Regulator Input
Installing the JP6 jumper will provide power to the onboard 5-V regulator (REG1). It is recommended to
keep this jumper installed under all conditions.
keep this jumper installed under all conditions.
3.5
S1, S2, S3, and S4 – Input Control
These switches are connected to the inputs via the source select jumpers (JP3, JP4, JP5, and JP7).
Moving the switches towards J1 will place a “high” on the input pins corresponding to the switch. Moving
the switch towards J2 will place a “low” on the input pins corresponding to the switch. There is an "H"
marking on the PCB silkscreen. This is incorrect. The switch must be moved away from the "H" marking
for a logic "high" condition on the input pins.
Moving the switches towards J1 will place a “high” on the input pins corresponding to the switch. Moving
the switch towards J2 will place a “low” on the input pins corresponding to the switch. There is an "H"
marking on the PCB silkscreen. This is incorrect. The switch must be moved away from the "H" marking
for a logic "high" condition on the input pins.
3.6
Test Points
Test points are provided on all signals that connect to the pins of the DRV8835 or DRV8836. Refer to the
schematic and PCB drawings below.
schematic and PCB drawings below.
4
DRV8835/DRV8836 Evaluation Module
SLVU694 – March 2012
Copyright © 2012, Texas Instruments Incorporated