Техническая Спецификация для Texas Instruments Evaluation Module for Integrated 3.3V / 5V Power LDO with Clock Output TPS51103EVM TPS51103EVM
Модели
TPS51103EVM
3
Schematic
Schematic
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Figure 1. TPS51103EVM Power Stage/Control Schematic
Note:
For reference only; see the enclosed
for specific values.
Using the TPS51103EVM Integrated 3.3-V/5-V Power LDO with Clock Output
4
SLUU303A – JUNE 2008 – Revised SEPTEMBER 2008