Техническая Спецификация для Texas Instruments IC MCU 16B MSP430F2111IRGET VQFN-24 TID MSP430F2111IRGET
Модели
MSP430F2111IRGET
MSP430F21x1
SLAS439F
–
SEPTEMBER 2004
–
REVISED AUGUST 2011
Memory Organization
Table 10. Memory Organization
MSP430F2101
MSP430F2111
MSP430F2121
MSP430F2131
Memory
Size
1 KB Flash
2 KB Flash
4 KB Flash
8 KB Flash
Main: interrupt vector
Flash
0xFFFF to 0xFFE0
0xFFFF to 0xFFE0
0xFFFF to 0xFFE0
0xFFFF to 0xFFE0
Main: code memory
Flash
0xFFFF to 0xFC00
0xFFFF to 0xF800
0xFFFF to 0xF000
0xFFFF to 0xE000
Information memory
Size
256 Byte
256 Byte
256 Byte
256 Byte
Flash
0x10FF to 0x1000
0x10FF to 0x1000
0x10FF to 0x1000
0x10FF to 0x1000
Boot memory
Size
1 KB
1 KB
1 KB
1 KB
ROM
0x0FFF to 0x0C00
0x0FFF to 0x0C00
0x0FFF to 0x0C00
0x0FFF to 0x0C00
RAM
Size
128 B
128 B
256 Byte
256 Byte
0x027F to 0x0200
0x027F to 0x0200
0x02FF to 0x0200
0x02FF to 0x0200
Peripherals
16-bit
0x01FF to 0x0100
0x01FF to 0x0100
0x01FF to 0x0100
0x01FF to 0x0100
8-bit
0x0FF to 0x010
0x0FF to 0x010
0x0FF to 0x010
0x0FF to 0x010
8-bit SFR
0x0F to 0x00
0x0F to 0x00
0x0F to 0x00
0x0F to 0x00
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART serial
interface. Access to theMSP430memoryvia theBSLis protected by user-defined password.Abootstrap loader
security key is provided at address 0FFDEh to disable the BSL completely or to disable the erasure of the flash if
an invalid password is supplied. For complete description of the features of the BSL and its implementation, see
the MSP430 Programming Via the Bootstrap Loader User
interface. Access to theMSP430memoryvia theBSLis protected by user-defined password.Abootstrap loader
security key is provided at address 0FFDEh to disable the BSL completely or to disable the erasure of the flash if
an invalid password is supplied. For complete description of the features of the BSL and its implementation, see
the MSP430 Programming Via the Bootstrap Loader User
’
s Guide, literature number
.
Table 11. BSL Keys
BSLKEY
DESCRIPTION
00000h
Erasure of flash disabled if an invalid password is supplied
0AA55h
BSL disabled
any other value
BSL enabled
Table 12. BSL Function Pins
BSL FUNCTION
DW, PW, DGV PACKAGE PINS
RGE PACKAGE PINS
Data transmit
14 - P1.1
14 - P1.1
Data receive
10 - P2.2
8 - P2.2
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in-system by the CPU. The
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include:
•
Flash memory has n segments of main memory and four segments of information memory (A to D) of
64 bytes each. Each segment in main memory is 512 bytes in size.
64 bytes each. Each segment in main memory is 512 bytes in size.
•
Segments 0 to n may be erased in one step, or each segment may be individually erased.
•
Segments A to D can be erased individually, or as a group with segments 0 to n.
Segments A to D are also called information memory.
Segments A to D are also called information memory.
•
Segment A contains calibration data. After reset, segment A is protected against programming and erasing. It
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
can be unlocked, but care should be taken not to erase this segment if the device-specific calibration data is
required.
10
Copyright
©
2004
–
2011, Texas Instruments Incorporated