Техническая Спецификация для Microchip Technology TMPSNS-RTD1
MCP6S21/2/6/8
DS21117B-page 4
2003-2012 Microchip Technology Inc.
DIGITAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, T
A
= +25°C, V
DD
= +2.5V to +5.5V, V
SS
= GND, V
REF
= V
SS
, G = +1 V/V,
Input = CH0 = (0.3V)/G, CH1 to CH7 = 0.3V, R
L
= 10 k
to V
DD
/2, C
L
= 60 pF, SI and SCK are tied low, and CS is tied high.
Parameters
Sym
Min
Typ
Max
Units
Conditions
SPI Inputs (CS, SI, SCK)
Logic Threshold, Low
V
IL
0
—
0.3V
DD
V
Input Leakage Current
I
IL
-1.0
—
+1.0
µA
Logic Threshold, High
V
IH
0.7V
DD
—
V
DD
V
Amplifier Output Leakage Current
—
-1.0
—
+1.0
µA
In Shutdown mode
SPI Output (SO, for MCP6S26 and MCP6S28)
Logic Threshold, Low
V
OL
V
SS
—
V
SS
+0.4
V
I
OL
= 2.1 mA, V
DD
= 5V
Logic Threshold, High
V
OH
V
DD
-0.5
—
V
DD
V
I
OH
= -400 µA
SPI Timing
Pin Capacitance
C
PIN
—
10
—
pF
All digital I/O pins
Input Rise/Fall Times (CS, SI, SCK)
t
RFI
—
—
2
µs
Output Rise/Fall Times (SO)
t
RFO
—
5
—
ns
MCP6S26 and MCP6S28
CS high time
t
CSH
40
—
—
ns
SCK edge to CS fall setup time
t
CS0
10
—
—
ns
SCK edge when CS is high
CS fall to first SCK edge setup time
t
CSSC
40
—
—
ns
SCK Frequency
f
SCK
—
—
10
MHz
V
DD
= 5V (Note 2)
SCK high time
t
HI
40
—
—
ns
SCK low time
t
LO
40
—
—
ns
SCK last edge to CS rise setup time
t
SCCS
30
—
—
ns
CS rise to SCK edge setup time
t
CS1
100
—
—
ns
SCK edge when CS is high
SI set-up time
t
SU
40
—
—
ns
SI hold time
t
HD
10
—
—
ns
SCK to SO valid propagation delay
t
DO
—
—
80
ns
MCP6S26 and MCP6S28
CS rise to SO forced to zero
t
SOZ
—
—
80
ns
MCP6S26 and MCP6S28
Channel and Gain Select Timing
Channel Select Time
t
CH
—
1.5
—
µs
CHx = 0.6V, CHy =0.3V, G = 1,
CHx to CHy select
CS = 0.7V
CHx to CHy select
CS = 0.7V
DD
to V
OUT
90% point
Gain Select Time
t
G
—
1
—
µs
CHx = 0.3V, G = 5 to G = 1 select,
CS = 0.7V
CS = 0.7V
DD
to V
OUT
90% point
Shutdown Mode Timing
Out of Shutdown mode (CS goes
high) to Amplifier Output Turn-on
Time
high) to Amplifier Output Turn-on
Time
t
ON
—
3.5
10
µs
CS = 0.7V
DD
to V
OUT
90% point
Into Shutdown mode (CS goes high)
to Amplifier Output High-Z Turn-off
Time
to Amplifier Output High-Z Turn-off
Time
t
OFF
—
1.5
—
µs
CS = 0.7V
DD
to V
OUT
90% point
POR Timing
Power-On Reset power-up time
t
RPU
—
30
—
µs
V
DD
= V
POR
- 0.1V to V
POR
+ 0.1V,
50% V
DD
to 90% V
OUT
point
Power-On Reset power-down time
t
RPD
—
10
—
µs
V
DD
= V
POR
+ 0.1V to V
POR
- 0.1V,
50% V
DD
to 90% V
OUT
point
Note
1: Not tested in production. Set by design and characterization.
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
2: When using the device in the daisy chain configuration, maximum clock frequency is determined by a combination of
propagation delay time (t
DO
80 ns), data input setup time (t
SU
40 ns), SCK high time (t
HI
40 ns), and SCK rise and
fall times of 5 ns. Maximum f
SCK
is, therefore,
5.8 MHz.