Техническая Спецификация для Microchip Technology MA330018
© 2007-2012 Microchip Technology Inc.
DS70291G-page 35
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04
4.0
MEMORY ORGANIZATION
The dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 and dsPIC33FJ128MCX02/X04 architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access to program memory from the data space during
code execution.
X04 and dsPIC33FJ128MCX02/X04 architecture
features separate program and data memory spaces
and buses. This architecture also allows the direct
access to program memory from the data space during
code execution.
4.1
Program Address Space
The program address memory space of the
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04
and dsPIC33FJ128MCX02/X04 devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in
dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04
and dsPIC33FJ128MCX02/X04 devices is 4M
instructions. The space is addressable by a 24-bit
value derived either from the 23-bit Program Counter
(PC) during program execution, or from table operation
or data space remapping as described in
.
User application access to the program memory space
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory map for the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 devices is shown in
is restricted to the lower half of the address range
(0x000000 to 0x7FFFFF). The exception is the use of
TBLRD/TBLWT operations, which use TBLPAG<7> to
permit access to the Configuration bits and Device ID
sections of the configuration memory space.
The memory map for the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and dsPIC33FJ128MCX02/
X04 devices is shown in
.
FIGURE 4-1:
PROGRAM MEMORY MAP FOR dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/
X04 AND dsPIC33FJ128MCX02/X04 DEVICES
X04 AND dsPIC33FJ128MCX02/X04 DEVICES
Note:
This data sheet summarizes the features
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70203) of the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip web site
(
of the dsPIC33FJ32MC302/304,
dsPIC33FJ64MCX02/X04 and
dsPIC33FJ128MCX02/X04 family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Program
Memory” (DS70203) of the “dsPIC33F/
PIC24H Family Reference Manual”, which
is available from the Microchip web site
(
www.microchip.com
).
Reset Address
0x000000
0x0000FE
0x000002
0x000100
Device Configuration
User Program
Flash Memory
(11264 instructions)
0x800000
0xF80000
Registers
0xF80017
0xF80018
0xF80018
DEVID (2)
0xFEFFFE
0xFF0000
0xFF0002
0xFF0002
0xF7FFFE
Unimplemented
(Read ‘0’s)
GOTO Instruction
0x000004
Reserved
0x7FFFFE
Reserved
0x000200
0x0001FE
0x000104
Alternate Vector Table
Reserved
Interrupt Vector Table
dsPIC33FJ32MC302/304
Conf
igur
ati
on Memory S
pace
User Memor
y S
pace
Note:
Memory areas are not shown to scale.
Reset Address
Device Configuration
User Program
Flash Memory
(22016 instructions)
Registers
DEVID (2)
Unimplemented
(Read ‘0’s)
GOTO Instruction
Reserved
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
dsPIC33FJ64MCX02/X04
Reset Address
Device Configuration
User Program
Flash Memory
(44032 instructions)
Registers
DEVID (2)
Unimplemented
(Read ‘0’s)
GOTO Instruction
Reserved
Reserved
Alternate Vector Table
Reserved
Interrupt Vector Table
dsPIC33FJ128MCX02/X04
0x0057FE
0x005800
0x005800
0x015800
0x0157FE
0x00AC00
0x00ABFE
Reserved
Reserved
Reserved
0xFFFFFE