Техническая Спецификация для Texas Instruments PGA450-Q1 Evaluation Module PGA450Q1EVM PGA450Q1EVM
Модели
PGA450Q1EVM
GPIO1
GPIO2
GPIO2
TXD
LIN
XOUT
SDO
SDI
SDI
CS
SCLK
TESTO_A
TESTO_D
RBIAS
RBIAS
CIN
IN
LIM
IN
LIM
XIN
DVDD
GND
VREG
RXD
AVDD
VREF
VREF
GND
GND
OUTB
OUTA
GPIO1
GPIO2
GPIO2
TXD
LIN
OUTB
SDO
SDI
SDO
SDI
CS
SCLK
TESTO_D
VPWR
GND
RBIAS
XIN
XOUT
XOUT
RXD
CIN
IN
IN
OUTA
VREF
VP_OTP
VP_OTP
AVDD
LIM
DVDD
GND
TESTO_A
VREG
GND
VPWR
1
VREG
2
LIN
3
GND
4
DVDD
5
XIN
6
XOUT
7
GPIO1
8
GPIO2
9
RxD
10
TxD
11
CIN
12
IN
13
LIM
14
GND
15
TESTO_A
16
RBIAS
17
TESTO_D
18
NCS
19
SCLK
20
SDI
21
SDO
22
OUTB
23
GND
24
OUTA
25
VPROG_OTP
26
VREF
27
AVDD
28
TPIC8500-Q1
U2
SDO
SDI
SCLK
SDI
SCLK
VPWR
GND
VP_OTP_SOC
AVDD_SOC
DVDD_SOC
GND
GND
VPWR
1
VREG
2
LIN
3
GND
4
DVDD
5
XIN
6
XOUT
7
GPIO1
8
GPIO2
9
RxD
10
TxD
11
CIN
12
IN
13
LIM
14
GND
15
TESTO_A
16
RBIAS
17
TESTO_D
18
NCS
19
SCLK
20
SDI
21
SDO
22
OUTB
23
GND
24
OUTA
25
VPROG_OTP
26
VREF
27
AVDD
28
TPIC8500-Q1
TI to supply, NO PIN1 DESIGNATOR - REVERSABLE
TI to supply, NO PIN1 DESIGNATOR - REVERSABLE
U3
VPWR
VP_OTP
GND
C11
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
VPWR
VREG
DVDD
CIN
VP_OTP
AVDD
C12
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C13
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C14
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C15
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C16
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
GND
GND
GND
GND
GND
R7
100.0k,0603,1/10W,0.1%,+-25ppm/C
RBIAS
GND
GND
C6
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
VPWR
VREG_SOC
DVDD_SOC VP_OTP_SOCAVDD_SOC
C7
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C8
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C9
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
C10
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
GND
GND
GND
GND
XIN
XOUT
NX3225SA-16.000000MHZ
1
3
4
2
X1
16MHz,15ppm,8pF
C17
12pF,0603,100V,5%,NPO
C18
12pF,0603,100V,5%,NPO
GND
GND
1
6
3
4
2
TI to supply
TR1
TRANSFORMER
XFMR RETURN
VREG
GND
OUTB
OUTA
Temperature Compensation Cap for the XDCR
Match to the Selected XDCR
Match to the Selected XDCR
C21
100uF,SMT,35V,20%,AL
1
1
2
2
P5
OUTPUT
C20
1500pF,0805,250V,20%,NPO
JP3
XFRM
GND
LIM
IN
XFMR RETURN
C19
0
.1
u
F
,0
6
0
3
,5
0
V
,1
0
%
,X
7
R
CS_SOCKET
RBIAS_SOC
GND
RBIAS_SOC
R9
3.3k,1210,1/4W,5%,+-200ppm/C
3.3k,1210,1/4W,5%,+-200ppm/C
R8
100.0k,0603,1/10W,0.1%,+-25ppm/C
VREG_SOC
R10
2
0
0
k
,0
6
0
3
,1
/1
0
W
,5
%
GND
VREG
1
1
2
2
DO NOT POPULATE
P6
JP4
JP5
PGA450-Q1 EVM Schematics and Layout Drawings
Figure 17. Schematic, PGA450-Q1
23
SLDU007A – March 2012 – Revised January 2013
PGA450-Q1 EVM User’s Guide
Copyright © 2012–2013, Texas Instruments Incorporated