Техническая Спецификация для Microchip Technology GPIODM-KPLCD
PIC18F2455/2550/4455/4550
DS39632E-page 50
© 2009 Microchip Technology Inc.
FIGURE 4-3:
TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO V
DD
, V
DD
RISE < T
PWRT
)
FIGURE 4-4:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
DD
): CASE 1
FIGURE 4-5:
TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V
DD
): CASE 2
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
T
PWRT
T
OST
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
V
DD
MCLR
INTERNAL POR
PWRT TIME-OUT
OST TIME-OUT
INTERNAL RESET
T
PWRT
T
OST