Техническая Спецификация для Microchip Technology MA330026
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 118
2011-2014 Microchip Technology Inc.
REGISTER 7-22:
IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
bit 15
bit 8
U-0
R/W-1
R/W-0
R/W-0
U-0
R/W-1
R/W-0
R/W-0
—
INT2IP2
INT2IP1
INT2IP0
—
T5IP2
(
)
T5IP1
(
)
T5IP0
(
)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15-7
Unimplemented: Read as ‘0’
bit 6-4
INT2IP<2:0>: External Interrupt 2 Priority bits
111
= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001
•
•
001
= Interrupt is Priority 1
000
= Interrupt source is disabled
bit 3
Unimplemented: Read as ‘0’
bit 2-0
T5IP<2:0>: Timer5 Interrupt Priority bits
111
= Interrupt is Priority 7 (highest priority interrupt)
•
•
•
001
•
•
001
= Interrupt is Priority 1
000
= Interrupt source is disabled
Note 1:
These bits are available in dsPIC33FJ32(GP/MC)10X devices only.