Техническая Спецификация для Microchip Technology MA330026
2011-2014 Microchip Technology Inc.
DS70000652F-page 175
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
13.0
INPUT CAPTURE
The input capture module is useful in applications
requiring frequency (period) and pulse measurement.
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices support
up to three input capture channels.
requiring frequency (period) and pulse measurement.
The dsPIC33FJ16(GP/MC)101/102 and
dsPIC33FJ32(GP/MC)101/102/104 devices support
up to three input capture channels.
The input capture module captures the 16-bit value of
the selected Time Base register when an event occurs
on the ICx pin. The events that cause a capture event
are listed below in three categories:
the selected Time Base register when an event occurs
on the ICx pin. The events that cause a capture event
are listed below in three categories:
1.
Simple Capture Event modes:
• Capture timer value on every falling edge of
• Capture timer value on every falling edge of
input at ICx pin
• Capture timer value on every rising edge of
input at ICx pin
2.
Capture timer value on every edge (rising and
falling).
falling).
3.
Prescaler Capture Event modes:
• Capture timer value on every 4th rising edge
• Capture timer value on every 4th rising edge
of input at ICx pin
• Capture timer value on every 16th rising
edge of input at ICx pin
Each input capture channel can select one of two
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
16-bit timers (Timer2 or Timer3) for the time base.
The selected timer can use either an internal or
external clock.
Other operational features include:
• Device wake-up from capture pin during CPU
Sleep and Idle modes
• Interrupt on input capture event
• 4-word FIFO buffer for capture values:
• 4-word FIFO buffer for capture values:
- Interrupt optionally generated after 1, 2, 3 or
4 buffer locations are filled
• Use of input capture to provide additional sources
of external interrupts
FIGURE 13-1:
INPUT CAPTURE x BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the dsPIC33FJ16(GP/MC)101/102
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Input Capture”
(DS70198) in the “dsPIC33/PIC24 Family
Reference Manual”, which is available
from the Microchip web site
(
and dsPIC33FJ32(GP/MC)101/102/104
family devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to “Input Capture”
(DS70198) in the “dsPIC33/PIC24 Family
Reference Manual”, which is available
from the Microchip web site
(
www.microchip.com
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
ICxBUF
ICx Pin
ICM<2:0> (ICxCON<2:0>)
Mode Select
Mode Select
3
Set Flag ICxIF
(in IFSn Register)
TMR2 TMR3
Edge Detection Logic
16
16
ICI<1:0>
ICOV, ICBNE (ICxCON<4:3>)
ICxCON
Interrupt
Logic
System Bus
From 16-Bit Timers
ICTMR
(ICxCON<7>)
(ICxCON<7>)
FI
FO
Prescaler
Counter
(1, 4, 16)
and
Clock Synchronizer
Note: An ‘x’ in a signal, register or bit name denotes the number of the input capture channel.
FIFO
R/W Logic
1
0