Техническая Спецификация для Microchip Technology MA330026
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
DS70000652F-page 178
2011-2014 Microchip Technology Inc.
14.1
Output Compare Modes
Configure the Output Compare modes by setting the
appropriate Output Compare Mode bits (OCM<2:0>) in
the Output Compare x Control (OCxCON<2:0>)
register.
appropriate Output Compare Mode bits (OCM<2:0>) in
the Output Compare x Control (OCxCON<2:0>)
register.
lists the different bit settings for the
Output Compare modes.
illustrates the
output compare operation for various modes. The user
application must disable the associated timer when
writing to the Output Compare Control registers to
avoid malfunctions.
writing to the Output Compare Control registers to
avoid malfunctions.
TABLE 14-1:
OUTPUT COMPARE x MODES
FIGURE 14-2:
OUTPUT COMPARE x OPERATION
Note:
See “Output Compare” in the “dsPIC33/
PIC24 Family Reference Manual”
(DS70209) for OCxR and OCxRS register
restrictions.
PIC24 Family Reference Manual”
(DS70209) for OCxR and OCxRS register
restrictions.
OCM<2:0>
Mode
OCx Pin Initial State
OCx Interrupt Generation
000
Module Disabled
Controlled by GPIO register
—
001
Active-Low One-Shot
0
OCx Rising Edge
010
Active-High One-Shot
1
OCx Falling Edge
011
Toggle
Current output is maintained OCx Rising and Falling Edge
100
Delayed One-Shot
0
OCx Falling Edge
101
Continuous Pulse
0
OCx Falling Edge
110
PWM without Fault Protection
0
, if OCxR is zero
1
, if OCxR is non-zero
No Interrupt
111
PWM with Fault Protection
0
, if OCxR is zero
1
, if OCxR is non-zero
OCFA
Falling Edge for OC1 to OC4
OCxRS
TMRy
OCxR
Timer is Reset on
Period Match
Continuous Pulse Mode
(OCM<2:0> = 101)
PWM Mode
(OCM<2:0> = 110 or 111)
Active-Low One-Shot
(OCM<2:0> = 001)
Active-High One-Shot
(OCM<2:0> = 010)
Toggle Mode
(OCM<2:0> = 011)
Delayed One-Shot
(OCM<2:0> = 100)
Output Compare
Mode Enabled