Техническая Спецификация для Microchip Technology MA330026
2011-2014 Microchip Technology Inc.
DS70000652F-page 183
dsPIC33FJ16(GP/MC)101/102 AND dsPIC33FJ32(GP/MC)101/102/104
15.2
PWM Faults
The Motor Control PWM module incorporates up to two
Fault inputs, FLTA1 and FLTB1. These Fault inputs are
implemented with Class B safety features. These
features ensure that the PWM outputs enter a safe
state when either of the Fault inputs is asserted.
Fault inputs, FLTA1 and FLTB1. These Fault inputs are
implemented with Class B safety features. These
features ensure that the PWM outputs enter a safe
state when either of the Fault inputs is asserted.
The FLTA1 and FLTB1 pins, when enabled and having
ownership of a pin, also enable a soft internal pull-down
resistor. The soft pull-down provides a safety feature by
automatically asserting the Fault should a break occur
in the Fault signal connection.
ownership of a pin, also enable a soft internal pull-down
resistor. The soft pull-down provides a safety feature by
automatically asserting the Fault should a break occur
in the Fault signal connection.
The implementation of internal pull-down resistors is
dependent on the device variant.
dependent on the device variant.
describes
which devices and pins implement the internal pull-down
resistors.
resistors.
TABLE 15-1:
INTERNAL PULL-DOWN
RESISTORS ON PWM FAULT
PINS
RESISTORS ON PWM FAULT
PINS
On devices without internal pull-downs on the Fault pin,
it is recommended to connect an external pull-down
resistor for Class B safety features.
it is recommended to connect an external pull-down
resistor for Class B safety features.
15.2.1
PWM FAULTS AT RESET
During any Reset event, the PWM module maintains
ownership of both PWM Fault pins. At Reset, both
Faults are enabled in latched mode to guarantee the
fail-safe power-up of the application. The application
software must clear both of the PWM Faults before
enabling the Motor Control PWM module.
ownership of both PWM Fault pins. At Reset, both
Faults are enabled in latched mode to guarantee the
fail-safe power-up of the application. The application
software must clear both of the PWM Faults before
enabling the Motor Control PWM module.
The Fault condition must be cleared by the external cir-
cuitry driving the Fault input pin high and clearing the
Fault interrupt flag. After the Fault pin condition has been
cleared, the PWM module restores the PWM output
signals on the next PWM period or half-period boundary.
cuitry driving the Fault input pin high and clearing the
Fault interrupt flag. After the Fault pin condition has been
cleared, the PWM module restores the PWM output
signals on the next PWM period or half-period boundary.
Refer to “Motor Control PWM” (DS70187) in the
“dsPIC33/PIC24 Family Reference Manual” for more
information on the PWM Faults.
“dsPIC33/PIC24 Family Reference Manual” for more
information on the PWM Faults.
15.3
Write-Protected Registers
On dsPIC33FJ(16/32)MC10X devices, write protection
is implemented for the PWMxCON1, PxFLTACON and
PxFLTBCON registers. The write protection feature
prevents any inadvertent writes to these registers. The
write protection feature can be controlled by the
PWMLOCK Configuration bit in the FOSCSEL Config-
uration register. The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protec-
tion feature can be disabled by configuring PWMLOCK
(FOSCSEL<6>) = 0.
is implemented for the PWMxCON1, PxFLTACON and
PxFLTBCON registers. The write protection feature
prevents any inadvertent writes to these registers. The
write protection feature can be controlled by the
PWMLOCK Configuration bit in the FOSCSEL Config-
uration register. The default state of the write protection
feature is enabled (PWMLOCK = 1). The write protec-
tion feature can be disabled by configuring PWMLOCK
(FOSCSEL<6>) = 0.
The user application can gain access to these locked
registers either by configuring the PWMLOCK bit
(FOSCSEL<6>) = 0 or by performing the unlock
sequence. To perform the unlock sequence, the user
application must write two consecutive values
(0xABCD and 0x4321) to the PWMxKEY register to
perform the unlock operation. The write access to the
PWMxCON1, PxFLTACON or PxFLTBCON registers
must be the next SFR access following the unlock
process. There can be no other SFR accesses during
the unlock process and subsequent write access.
registers either by configuring the PWMLOCK bit
(FOSCSEL<6>) = 0 or by performing the unlock
sequence. To perform the unlock sequence, the user
application must write two consecutive values
(0xABCD and 0x4321) to the PWMxKEY register to
perform the unlock operation. The write access to the
PWMxCON1, PxFLTACON or PxFLTBCON registers
must be the next SFR access following the unlock
process. There can be no other SFR accesses during
the unlock process and subsequent write access.
To write to all registers, the PWMxCON1, PxFLTACON
and PxFLTBCON registers require three unlock
operations.
and PxFLTBCON registers require three unlock
operations.
The correct unlocking sequence is described in
and
Device
Fault Pin
Internal
Pull-Down
Implemented?
dsPIC33FJXXMC101
FLTA1
No
dsPIC33FJXXMC102
FLTA1
Yes
FLTB1
Yes
dsPIC33FJ32MC104
FLTA1
Yes
FLTB1
Yes
Note:
The number of PWM Faults mapped to
the device pins depend on the specific
variant. Regardless of the variant, both
Faults will be enabled during any Reset
event. The application must clear both
FLTA1 and FLTB1 before enabling the
Motor Control PWM module. Refer to the
specific device pin diagrams to see which
Fault pins are mapped to the device pins.
the device pins depend on the specific
variant. Regardless of the variant, both
Faults will be enabled during any Reset
event. The application must clear both
FLTA1 and FLTB1 before enabling the
Motor Control PWM module. Refer to the
specific device pin diagrams to see which
Fault pins are mapped to the device pins.