Техническая Спецификация для Microchip Technology ARD00385
2009-2011 Microchip Technology Inc.
DS39957D-page 205
PIC18F87K90 FAMILY
15.2
Timer3/5/7 Operation
Timer3, Timer5 and Timer7 can operate in these
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
• Timer with Gated Control
The operating mode is determined by the clock select
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (F
bits, TMRxCSx (TxCON<7:6>). When the TMRxCSx bits
are cleared (= 00), Timer3/5/7 increments on every inter-
nal instruction cycle (F
OSC
/4). When TMRxCSx = 01, the
Timer3/5/7 clock source is the system clock (F
OSC
), and
when it is ‘10’, Timer3/5/7 works as a counter from the
external clock on the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
external clock on the TxCKI pin (on the rising edge after
the first falling edge) or the SOSC oscillator.
FIGURE 15-1:
TIMER3/5/7 BLOCK DIAGRAM
TMRxH
TMRxL
TxSYNC
TxCKPS<1:0>
Prescaler
1, 2, 4, 8
0
1
Synchronized
Clock Input
2
Set Flag bit
TMRxIF on
Overflow
TMRxIF on
Overflow
TMRx
(2)
TMRxON
Note
1:
The ST buffer is high-speed type when using TxCKI.
2:
Timerx registers increment on the rising edge.
3:
Synchronization does not operate while in Sleep.
TxG
TxOSC
F
OSC
/4
Internal
Clock
SOSCO
SOSCI
SOSCEN
1
0
TxCKI
TMRxCS<1:0>
(1)
Synchronize
(3)
det
Sleep Input
TMRxGE
0
1
00
01
10
11
From TMR(x + 1)
From Comp. 1
TxGPOL
D
Q
CK
Q
0
1
TxGVAL
TxGTM
Single Pulse
Acq. Control
TxGSPM
TxGGO/TxDONE
TxGSS<1:0>
EN
OUT
10
00
01
F
OSC
Internal
Clock
From Comp. 2
Output
Match PR(x + 1)
R
D
EN
Q
Q1
RD
T3GCON
Data Bus
det
Interrupt
TMRxGIF
Set
TxCLK
F
OSC
/2
Internal
Clock
D
EN
Q
TxG_IN
TMRxON
Output