Техническая Спецификация для Microchip Technology ARD00385
2009-2011 Microchip Technology Inc.
DS39957D-page 247
PIC18F87K90 FAMILY
18.4
PWM Mode
In Pulse-Width Modulation (PWM) mode, the CCP4 pin
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP4 pin an output.
produces up to a 10-bit resolution PWM output. Since
the CCP4 pin is multiplexed with a PORTC or PORTE
data latch, the appropriate TRIS bit must be cleared to
make the CCP4 pin an output.
shows a simplified block diagram of the
ECCP1 module in PWM mode.
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
For a step-by-step procedure on how to set up the CCP
module for PWM operation, see
.
FIGURE 18-3:
SIMPLIFIED PWM BLOCK
DIAGRAM
DIAGRAM
CCP6CON
—
—
DC6B1
DC6B0
CCP6M3
CCP6M2 CCP6M1 CCP6M0
CCP7CON
—
—
DC7B1
DC7B0
CCP7M3
CCP7M2 CCP7M1 CCP7M0
CCP8CON
—
—
DC8B1
DC8B0
CCP8M3
CCP8M2 CCP8M1 CCP8M0
CCP9CON
)
—
—
DC9B1
DC9B0
CCP9M3
CCP9M2 CCP9M1 CCP9M0
CCP10CON
)
—
—
DC10B1
DC10B0
CCP10M3 CCP10M2 CCP10M1 CCP10M0
CCPTMRS1
C7TSEL1 C7TSEL0
—
C6TSEL0
—
C5TSEL0 C4TSEL1 C4TSEL0
CCPTMRS2
—
—
—
C10TSEL0
—
C9TSEL0 C8TSEL1 C8TSEL0
TABLE 18-5:
REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 (CONTINUED)
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
Values
on Page:
Legend:
— = unimplemented, read as ‘0’. Shaded cells are not used by Capture/Compare or Timer1/3/5/7.
Note 1:
Unimplemented in devices with a program memory of 32 Kbytes (PIC18FX5K90).
2:
Unimplemented in 64-pin devices.
Note:
Clearing the CCP4CON register will force
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
the RC1 or RE7 output latch (depending
on device configuration) to the default low
level. This is not the PORTC or PORTE
I/O data latch.
CCPR4L
CCPR4H (Slave)
Comparator
TMR2
Comparator
PR2
(Note 1)
R
Q
S
Duty Cycle Registers
CCP4CON<5:4>
Clear Timer,
ECCP1 Pin and
ECCP1 Pin and
Latch D.C.
TRISC<2>
RC2/ECCP1
Note 1:
The 8-bit TMR2 value is concatenated with the 2-bit
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
internal Q clock, or 2 bits of the prescaler, to create
the 10-bit time base.
2:
CCP4 and its appropriate timers are used as an
example. For details on all of the CCP modules and
their timer assignments, see
example. For details on all of the CCP modules and
their timer assignments, see
.
(Note 2)
(Note 2)