Техническая Спецификация для Microchip Technology ARD00385

 2009-2011 Microchip Technology Inc.

DS39957D-page 271

19.4.8

OPERATION IN POWER-MANAGED 
MODES

In Sleep mode, all clock sources are disabled.
Timer2/4/6/8 will not increment and the state of the
module will not change. If the ECCPx pin is driving a
value, it will continue to drive that value. When the
device wakes up, it will continue from this state. If
Two-Speed Start-ups are enabled, the initial start-up
frequency from HF-INTOSC and the postscaler may
not be immediately stable.
In PRI_IDLE mode, the primary clock will continue to
clock the ECCPx module without change.

19.4.8.1

Operation with Fail-Safe 
Clock Monitor (FSCM)

If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock
failure will force the device into the power-managed
RC_RUN mode and the OSCFIF bit of the PIR2/4/6/8
register will be set. The ECCPx will then be clocked from
the internal oscillator clock source, which may have a
different clock frequency than the primary clock.

19.4.9

EFFECTS OF A RESET

Both Power-on Reset and subsequent Resets will force
all ports to Input mode and the ECCP registers to their
Reset states. This forces the ECCP module to reset to
a state compatible with previous, non-Enhanced CCP
modules used on other PIC18 and PIC16 devices.