Техническая Спецификация для Microchip Technology ARD00385
2009-2011 Microchip Technology Inc.
DS39957D-page 85
PIC18F87K90 FAMILY
6.0
MEMORY ORGANIZATION
PIC18F87K90 family devices have these types of
memory:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses. This enables
concurrent access of the two memory spaces.
memory:
• Program Memory
• Data RAM
• Data EEPROM
As Harvard architecture devices, the data and program
memories use separate busses. This enables
concurrent access of the two memory spaces.
The data EEPROM, for practical purposes, can be
regarded as a peripheral device because it is
addressed and accessed through a set of control
registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”
regarded as a peripheral device because it is
addressed and accessed through a set of control
registers.
Additional detailed information on the operation of the
Flash program memory is provided in Section 7.0
“Flash Program Memory”
. The data EEPROM is
discussed separately in Section 8.0 “Data EEPROM
Memory”
Memory”
FIGURE 6-1:
MEMORY MAPS FOR PIC18F87K90 FAMILY DEVICES
Note:
Sizes of memory areas are not to scale. The sizes of program memory areas are enhanced to show detail.
Unimplemented
Read as ‘0’
Unimplemented
Read as ‘0’
000000h
1FFFFFh
01FFFFh
00FFFFh
PC<20:0>
Stack Level 1
Stack Level 31
CALL, CALLW, RCALL,
RETURN, RETFIE, RETLW,
RETURN, RETFIE, RETLW,
21
Us
er M
e
mo
ry
S
pace
On-Chip
Memory
On-Chip
Memory
ADDULNK, SUBULNK
PIC18FX6K90
PIC18FX7K90
Unimplemented
Read as ‘0’
On-Chip
Memory
PIC18FX5K90
007FFFh