Техническая Спецификация для STMicroelectronics M48Z12-150PC1 Memory IC M48Z12-150PC1
Модели
M48Z12-150PC1
Operation modes
M48Z02, M48Z12
Doc ID 2420 Rev 9
Figure 4.
READ mode AC waveforms
Note:
WRITE enable (W) = high.
Table 3.
READ mode AC characteristics
2.2 WRITE
mode
The M48Z02/12 is in the WRITE mode whenever W and E are active. The start of a WRITE
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
is referenced from the latter occurring falling edge of W or E. A WRITE is terminated by the
earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W
must return high for a minimum of t
EHAX
from chip enable or t
WHAX
from WRITE enable prior
to the initiation of another READ or WRITE cycle. Data-in must be valid t
DVWH
prior to the
end of WRITE and remain valid for t
WHDX
afterward. G should be kept high during WRITE
cycles to avoid bus contention; although, if the output bus has been activated by a low on E
and G, a low on W will disable the outputs t
and G, a low on W will disable the outputs t
WLQZ
after W falls.
Symbol
Parameter
(1)
1.
Valid for ambient operating temperature: T
A
= 0 to 70 °C or –40 to 85 °C; V
CC
= 4.75 to 5.5 V or 4.5 to 5.5 V (except where
noted).
M48Z02/M48Z12
Unit
–70
–150
–200
Min
Max
Min
Max
Min
Max
t
AVAV
READ cycle time
70
150
200
ns
t
AVQV
Address valid to output valid
70
150
200
ns
t
ELQV
Chip enable low to output valid
70
150
200
ns
t
GLQV
Output enable low to output valid
35
75
80
ns
t
ELQX
Chip enable low to output transition
5
10
10
ns
t
GLQX
Output enable low to output transition
5
5
5
ns
t
EHQZ
Chip enable high to output Hi-Z
25
35
40
ns
t
GHQZ
Output enable high to output Hi-Z
25
35
40
ns
t
AXQX
Address transition to output transition
10
5
5
ns
AI01330
tAVAV
tAVQV
tAXQX
tELQV
tELQX
tEHQZ
tGLQV
tGLQX
tGHQZ
VALID
A0-A10
E
G
DQ0-DQ7
VALID