Техническая Спецификация для Microchip Technology TDGL002 - chipKIT Uno32 Development Board TDGL002 TDGL002
Модели
TDGL002
© 2011 Microchip Technology Inc.
DS61143H-page 95
PIC32MX3XX/4XX
9.0
PREFETCH CACHE
Prefetch cache increases performance for applications
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
executing out of the cacheable program Flash memory
regions by implementing instruction caching, constant
data caching and instruction prefetching.
9.1
Features
• 16 Fully Associative Lockable Cache Lines
• 16-byte Cache Lines
• Up to four Cache Lines Allocated to Data
• Two Cache Lines with Address Mask to hold
repeated instructions
• Pseudo LRU replacement policy
• All Cache Lines are software writable
• 16-byte parallel memory fetch
• Predictive Instruction Prefetch
FIGURE 9-1:
PREFETCH MODULE BLOCK DIAGRAM
Note 1: This data sheet summarizes the features
of the PIC32MX3XX/4XX family of
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) of the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(
devices. It is not intended to be a
comprehensive reference source. To
complement the information in this data
sheet, refer to Section 4. “Prefetch
Cache” (DS61119) of the “PIC32 Family
Reference Manual”, which is available
from the Microchip web site
(
www.microchip.com/PIC32
).
2: Some registers and associated bits
described in this section may not be
available on all devices. Refer to
available on all devices. Refer to
in
this data sheet for device-specific register
and bit information.
and bit information.
CTRL
RDATA
Prefetch
Prefetch
Hit Logic
Cache
Line
Address
Encode
Cache Line
FSM
CTRL
RDATA
Tag Logic
Bus Control
Cache Control
Prefetch Control
Hit LRU
Miss LRU
BMX/CPU
BMX/CPU
CTRL
PFM