Техническая Спецификация для Microchip Technology MA330028
2011-2013 Microchip Technology Inc.
DS70000657H-page 269
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X AND PIC24EPXXXGP/MC20X
bit 1
SPITBF:
SPIx Transmit Buffer Full Status bit
1
= Transmit not yet started, SPIxTXB is full
0
= Transmit started, SPIxTXB is empty
Standard Buffer mode:
Automatically set in hardware when core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
Automatically set in hardware when core writes to the SPIxBUF location, loading SPIxTXB.
Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR.
Enhanced Buffer mode:
Automatically set in hardware when the CPU writes to the SPIxBUF location, loading the last available
buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write
operation.
bit 0
SPIRBF:
SPIx Receive Buffer Full Status bit
1
= Receive is complete, SPIxRXB is full
0
= Receive is incomplete, SPIxRXB is empty
Standard Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.
Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically
cleared in hardware when the core reads the SPIxBUF location, reading SPIxRXB.
Enhanced Buffer mode:
Automatically set in hardware when SPIx transfers data from SPIxSR to the buffer, filling the last unread
buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from
SPIxSR.
REGISTER 18-1:
SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED)