Техническая Спецификация для Microchip Technology DM164134
© 2006 Microchip Technology Inc.
DS41159E-page 21
PIC18FXX8
2.6.2
OSCILLATOR TRANSITIONS
The PIC18FXX8 devices contain circuitry to prevent
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
“glitches” when switching between oscillator sources.
Essentially, the circuitry waits for eight rising edges of
the clock source that the processor is switching to. This
ensures that the new clock source is stable and that its
pulse width will not be less than the shortest pulse
width of the two clock sources.
Figure 2-7 shows a timing diagram indicating the tran-
sition from the main oscillator to the Timer1 oscillator.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator,
operation resumes. No additional delays are required
after the synchronization cycles.
sition from the main oscillator to the Timer1 oscillator.
The Timer1 oscillator is assumed to be running all the
time. After the SCS bit is set, the processor is frozen at
the next occurring Q1 cycle. After eight synchronization
cycles are counted from the Timer1 oscillator,
operation resumes. No additional delays are required
after the synchronization cycles.
The sequence of events that takes place when switch-
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
ing from the Timer1 oscillator to the main oscillator will
depend on the mode of the main oscillator. In addition
to eight clock cycles of the main oscillator, additional
delays may take place.
If the main oscillator is configured for an external
crystal (HS, XT, LP), the transition will take place after
an oscillator start-up time (T
crystal (HS, XT, LP), the transition will take place after
an oscillator start-up time (T
OST
) has occurred. A timing
diagram indicating the transition from the Timer1
oscillator to the main oscillator for HS, XT and LP
modes is shown in Figure 2-8.
oscillator to the main oscillator for HS, XT and LP
modes is shown in Figure 2-8.
FIGURE 2-7:
TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR
FIGURE 2-8:
TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS, XT, LP)
Q3
Q2
Q1
Q4
Q3
Q2
OSC1
Internal
SCS
(OSCCON<0>)
Program
PC + 2
PC
Note 1: Delay on internal system clock is eight oscillator cycles for synchronization.
Q1
T1OSI
Q4
Q1
PC + 4
Q1
Tscs
Clock
Counter
System
Q2
Q3
Q4
Q1
T
DLY
T
T
1
P
T
OSC
2
1
3
4
5
6
7
8
Q3
Q3
Q4
Q1 Q2 Q3 Q4
Q1 Q2
OSC1
Internal System
SCS
(OSCCON<0>)
Program
PC
PC + 2
Note 1: T
OST
= 1024 T
OSC
(drawing not to scale).
T1OSI
Clock
OSC2
T
OST
Q1
PC + 4
T
T
1
P
T
OSC
T
SCS
1
2
3
4
5
6
7
8
Counter