Техническая Спецификация для Microchip Technology MA160014
PIC18(L)F2X/4XK22
DS41412F-page 292
2010-2012 Microchip Technology Inc.
FIGURE 16-12:
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
CREN bit
RXx/DTx
Write to
bit SREN
SREN bit
RCxIF bit
(Interrupt)
Read
RCREGx
‘0’
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
‘0’
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TXx/CKx pin
TXx/CKx pin
pin
(SCKP = 0)
(SCKP = 1)
TABLE 16-8:
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BAUDCON1
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN
BAUDCON2
ABDOVF
RCIDL
DTRXP
CKTXP
BRG16
—
WUE
ABDEN
INTCON
GIE/GIEH
PEIE/GIEL
TMR0IE
INT0IE
RBIE
TMR0IF
INT0IF
RBIF
IPR1
—
ADIP
RC1IP
TX1IP
SSP1IP
CCP1IP
TMR2IP
TMR1IP
IPR3
SSP2IP
BCL2IP
RC2IP
TX2IP
CTMUIP
TMR5GIP
TMR3GIP
TMR1GIP
PIE1
—
ADIE
RC1IE
TX1IE
SSP1IE
CCP1IE
TMR2IE
TMR1IE
PIE3
SSP2IE
BCL2IE
RC2IE
TX2IE
CTMUIE
TMR5GIE
TMR3GIE
TMR1GIE
PIR1
—
ADIF
RC1IF
TX1IF
SSP1IF
CCP1IF
TMR2IF
TMR1IF
PIR3
SSP2IF
BCL2IF
RC2IF
TX2IF
CTMUIF
TMR5GIF
TMR3GIF
TMR1GIF
PMD0
UART2MD UART1MD TMR6MD
TMR5MD
TMR4MD
TMR3MD
TMR2MD
TMR1MD
RCREG1
EUSART1 Receive Register
—
RCSTA1
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
RCREG2
EUSART2 Receive Register
—
RCSTA2
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRG1
EUSART1 Baud Rate Generator, Low Byte
—
SPBRGH1
EUSART1 Baud Rate Generator, High Byte
—
SPBRG2
EUSART2 Baud Rate Generator, Low Byte
—
SPBRGH2
EUSART2 Baud Rate Generator, High Byte
—
TXSTA1
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
TXSTA2
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for synchronous master reception.