Техническая Спецификация для Microchip Technology MA160014
2010-2012 Microchip Technology Inc.
DS41412F-page 327
PIC18(L)F2X/4XK22
19.3.2
CAPACITANCE CALIBRATION
There is a small amount of capacitance from the
internal A/D Converter sample capacitor as well as
stray capacitance from the circuit board traces and
pads that affect the precision of capacitance
measurements. A measurement of the stray
capacitance can be taken by making sure the desired
capacitance to be measured has been removed. The
measurement is then performed using the following
steps:
internal A/D Converter sample capacitor as well as
stray capacitance from the circuit board traces and
pads that affect the precision of capacitance
measurements. A measurement of the stray
capacitance can be taken by making sure the desired
capacitance to be measured has been removed. The
measurement is then performed using the following
steps:
1.
Initialize the A/D Converter and the CTMU.
2.
Set EDG1STAT (= 1).
3.
Wait for a fixed delay of time t.
4.
Clear EDG1STAT.
5.
Perform an A/D conversion.
6.
Calculate the stray and A/D sample capacitances:
where I is known from the current source measurement
step, t is a fixed delay and V is measured by performing
an A/D conversion.
step, t is a fixed delay and V is measured by performing
an A/D conversion.
This measured value is then stored and used for
calculations of time measurement or subtracted for
capacitance measurement. For calibration, it is
expected that the capacitance of C
calculations of time measurement or subtracted for
capacitance measurement. For calibration, it is
expected that the capacitance of C
STRAY
+ C
AD
is
approximately known. C
AD
is approximately 4 pF.
An iterative process may need to be used to adjust the
time, t, that the circuit is charged to obtain a reasonable
voltage reading from the A/D Converter. The value of t
may be determined by setting C
time, t, that the circuit is charged to obtain a reasonable
voltage reading from the A/D Converter. The value of t
may be determined by setting C
OFFSET
to a theoretical
value, then solving for t. For example, if C
STRAY
is
theoretically calculated to be 11 pF, and V is expected
to be 70% of V
to be 70% of V
DD
, or 2.31V, then t would be:
or 63
s.
See
for a typical routine for CTMU
capacitance calibration.
C
OFFSET
C
STRAY
C
AD
+
I t
V
=
=
(4 pF + 11 pF) • 2.31V/0.55
A