Техническая Спецификация для Freescale Semiconductor Accelerometer Cube Demo MMA9559LKUBE MMA9559LKUBE
Модели
MMA9559LKUBE
MMA955xL
Sensors
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc.
19
4.13
I
2
C Timing
This device includes a slave I
2
C module that can be used to control the sensor and can be active 100 percent of the time. It also
includes a master/slave I
2
C module that should be used only during CPU run mode (
D
).
Figure 9. I
2
C standard and fast-mode timing
4.13.1
Slave I
2
C
4.13.2
Master I
2
C Timing
The master I
2
C module should only be used when the system clock is running at full rate. Do not attempt to use the master I
2
C
module across frames in which a portion of the time is spent in low-speed mode.
Table 12. I
2
C Speed Ranges
Mode
Max Baud
Rate (f
SCL
)
Min
Bit Time
Min SCL Low
(t
LOW
)
Min SCL High
(t
HIGH
)
Min Data setup Time
(t
SU; DAT
)
Min/Max Data Hold Time
(t
HD; DAT
)
Standard
100 KHz
10
s
4.7
s
4
s
250 ns
0
s/3.45 s
(1)
1.
The maximum t
HD; DAT
must be at least a transmission time less than t
VD;DAT
or t
VD;ACK
. For details, see the I
2
C standard.
Fast
400 KHz
2.5
s
1.3
s
0.6
s
100 ns
0
s/0.9 s
(1)
Fast +
1 MHz
1
s
500 ns
260 ns
50 ns
0
s/0.45 s
(1)
High-speed
supported
2.0 MHz
0.5
s
200 ns
200 ns
10 ns
(2)
0 ns/70 ns (100 pf)
(2)
2.
Timing met with IFE = 0, DS = 1, and SE = 1. See the “Port Controls” chapter in the MMA955xL Three-Axis Accelerometer Reference Manual
(MMA955xLRM).
(MMA955xLRM).
Table 13. Master I
2
C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Min
Max
Min
Max
SCL clock frequency
f
SCL
0
100
0
400
kHz
Hold time (repeated) START condition. After this period, the first
clock pulse is generated.
clock pulse is generated.
t
HD; STA
4.0
—
0.6
—
s
LOW period of the SCL clock
t
LOW
4.7
—
1.3
—
s
HIGH period of the SCL clock
t
HIGH
4.0
—
0.6
—
s
Setup time for a repeated START condition
t
SU; STA
4.7
—
0.6
—
s
Data hold time for I
2
C-bus devices
t
HD; DAT
0
(1)
1.
The master mode I
2
C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves acknowledge this address byte, a neg-
ative hold time can result, depending on the edge rates of the SDA and SCL lines.
3.45
(2)
2.
The maximum t
HD;
DAT
must be met only if the device does not stretch the LOW period (t
LOW
) of the SCL signal.
0
s
Data setup time
t
SU; DAT
250
(3)
3.
Setup time in slave-transmitter mode is one IPBus clock period, if the TX FIFO is empty.
—
(4)
4.
A fast-mode I
2
C bus device can be used in a Standard mode I
2
C bus system, but the requirement t
SU; DAT
250 ns must then be met. This will automat-
ically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr
output the next data bit to the SDA line tr
max +
t
SU; DAT
= 1000 + 250 = 1250 ns (according to the Standard-mode I
2
C bus specification) before the SCL
line is released.
—
ns
Setup time for STOP condition
t
SU; STO
4.0
—
0.6
—
µs
Bus-free time between STOP and START condition
t
BUF
4.7
—
1.3
—
µs
Pulse width of spikes that must be suppressed by the input filter
t
SP
N/A
N/A
0
50
ns
SDA
SCL
t
HD; STA
t
HD; DAT
t
LOW
t
SU; DAT
t
HIGH
t
SU; STA
SR
P
S
S
t
HD; STA
t
SP
t
SU; STO
t
BUF
t
f
t
r
t
f
t
r