Техническая Спецификация для Freescale Semiconductor Tower System Kit for MC9S08PT60 Series TWR-S08PT60-KIT TWR-S08PT60-KIT

1

P

Bus frequency (t

cyc

 = 1/f

Bus

)

f

Bus

DC

—

20

MHz

2

P

Internal low power oscillator frequency

f

LPO

0.67

1.0

1.25

KHz

3

D

t

extrst

1.5 ×

t

Self_reset

—

—

ns

4

D

Reset low drive

t

rstdrv

34 × t

cyc

—

—

ns

5

D

BKGD/MS setup time after issuing background
debug force reset to enter user or BDM modes

t

MSSU

500

—

—

ns

6

D

BKGD/MS hold time after issuing background
debug force reset to enter user or BDM modes

t

MSH

100

—

—

ns

7

D

IRQ pulse width

Asynchronous

path

t

ILIH

100

—

—

ns

D

t

IHIL

1.5 × t

cyc

—

—

ns

8

D

Keyboard interrupt pulse

width

Asynchronous

path

t

ILIH

100

—

—

ns

D

Synchronous path

t

IHIL

1.5 × t

cyc

—

—

ns

9

C

Port rise and fall time -

Normal drive strength

(HDRVE_PTXx = 0) (load

—

t

Rise

—

10.2

—

ns

C

t

Fall

—

9.5

—

ns

C

Port rise and fall time -

Extreme high drive

strength (HDRVE_PTXx =

1) (load = 50 pF)

—

t

Rise

—

5.4

—

ns

C

t

Fall

—

4.6

—

ns

1. Typical values are based on characterization data at V

DD

 = 5.0 V, 25 °C unless otherwise stated.

2. This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3. To enter BDM mode following a POR, BKGD/MS must be held low during the powerup and for a hold time of t

MSH

 after

V

DD

 rises above V

LVD

.

4. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.

5. Timing is shown with respect to 20% V

DD

 and 80% V

DD

 levels. Temperature range -40 °C to 105 °C.

















t

extrst

RESET PIN

14

Freescale Semiconductor, Inc.