Техническая Спецификация для Freescale Semiconductor Tower System Kit for MC9S08PT60 Series TWR-S08PT60-KIT TWR-S08PT60-KIT

3. Monotonicity and no-missing-codes guaranteed in 10-bit and 8-bit modes

D

Supply voltage

V

DDA

2.7

—

5.5

V

T

Supply current (Operation mode)

I

DDA

—

10

20

µA

D

Analog input voltage

V

AIN

V

SS

 - 0.3

—

V

DDA

V

P

Analog input offset voltage

V

AIO

—

—

40

mV

C

Analog comparator hysteresis (HYST=0)

V

H

—

15

20

mV

C

Analog comparator hysteresis (HYST=1)

V

H

—

20

30

mV

T

Supply current (Off mode)

I

DDAOFF

—

60

—

nA

C

Propagation Delay

t

D

—

0.4

1

µs

The serial peripheral interface (SPI) provides a synchronous serial bus with master and
slave operations. Many of the transfer attributes are programmable. The following tables
provide timing characteristics for classic SPI timing modes. Refer to the SPI chapter of
the chip's reference manual for information about the modified transfer formats used for
communicating with slower peripheral devices. All timing is shown with respect to 20%
V

DD

 and 70% V

DD

, unless noted, and 100 pF load on all SPI pins. All timing assumes

slew rate control is disabled and high drive strength is enabled for SPI output pins.

1

f

op

Frequency of operation

f

Bus

/2048

f

Bus

/2

Hz

f

Bus

 is the bus

clock

2

t

SPSCK

SPSCK period

2 x t

Bus

2048 x t

Bus

ns

t

Bus

 = 1/f

Bus

3

t

Lead

Enable lead time

1/2

—

t

SPSCK

—

4

t

Lag

Enable lag time

1/2

—

t

SPSCK

—

5

t

WSPSCK

Clock (SPSCK) high or low time

t

Bus

 - 30

1024 x t

Bus

ns

—

Freescale Semiconductor, Inc.

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