Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO
Модели
MC56F8006DEMO
Memory Maps
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
31
On-chip RAM is also mapped into program space starting at P: 0x00 8000. This makes for easier online reprogramming of
on-chip flash.
on-chip flash.
Figure 8. 56F8006 Dual Port RAM Map
Figure 9. 56F8002 Dual Port RAM Map
5.4
Interrupt Vector Table and Reset Vector
The location of the vector table is determined by the vector base address register (VBA). The value in this register is used as
the upper 14 bits of the interrupt vector VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt
and are then appended onto VBA before presenting the full VAB to the core. Please see the MC56F8006 Peripheral Reference
Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different.
the upper 14 bits of the interrupt vector VAB[20:0]. The lower seven bits are determined based on the highest priority interrupt
and are then appended onto VBA before presenting the full VAB to the core. Please see the MC56F8006 Peripheral Reference
Manual for detail. The reset startup addresses of 56F8002 and 56F8006 are different.
•
56F8006 startup address is located at 0x00 0000. The reset value of VBA is reset to a value of 0x0000 that corresponds
to address 0x00 0000
to address 0x00 0000
•
56F8002 startup address is located at 0x00 0800. The reset value of VBA is reset to a value of 0x0010 that corresponds
to address 0x00 0800
to address 0x00 0800
By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR
instructions.
The highest number vector, a user assignable vector USER6 (vector 50), can be defined as a fast interrupt if the instruction
located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference
Manual for detail.
located in this vector location is not a JSR or BSR instruction. Please see section 9.3.3.3 of DSP56800E 16-Bit Core Reference
Manual for detail.
Reserved
RAM
Reserved
Reserved
EOnCE
Peripherals
Reserved
RAM
Dual Port RAM
Program
Data
Flash
0x00 0000
0x00 0400
0x00 F000
0x01 0000
0xFF FF00
0x00 0000
0x00 2000
0x00 8000
0x00 8400
Reserved
RAM
Reserved
Reserved
EOnCE
Peripherals
Reserved
RAM
Dual Port RAM
Program
Data
Flash
0x00 0000
0x00 0400
0x00 F000
0x01 0000
0xFF FF00
0x00 0000
0x00 0800
0x00 8000
0x00 8400
Reserved
0x00 2000