Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO

Freescale Semiconductor

38

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Registers containing the JTAG ID of the chip

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Controls for programmable peripheral and GPIO connections

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Peripheral clocks for TMR and PWM and SCI with a high-speed (3X) option

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Power-saving clock gating for peripherals

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Controls the enable/disable functions of large regulator standby mode with write protection capability 

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Permits selected peripherals to run in stop mode to generate stop recovery interrupts

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Controls for programmable peripheral and GPIO connections

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Software chip reset

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I/O short address base location control

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Peripheral protection control to provide runaway code protection for safety-critical applications

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Controls output of internal clock sources to CLKO pin

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Four general-purpose software control registers are reset only at power-on

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Peripherals stop mode clocking control

The comparators, timers, and PWM_reload_sync output can be connected to the programmable delay block (PDB) trigger input. 
The PDB pre-trigger A and trigger A outputs are connected to the ADCA and PGA0 hardware trigger inputs. The PDB 
pre-trigger B and trigger B outputs are connected to the ADCB and PGA1 hardware trigger inputs. When the input trigger of 
PDB is asserted, PDB trigger and pre-trigger outputs are asserted after a delay of a pre-programmed period. See the MC56F8006 
Peripheral Reference Manual for additional information.

TriggerA

 

Pre-
TriggerA 

TriggerB

 

+

–

PGA0 Controller

ANA15

ANA9

ANA7

ADHWT

ADCA 
Trigger

SSEL[0]

SSEL[1]

ADCA

+

–

PGA1 Controller

ANB15 ANB8

ANB6

ADHWT

ADCB 
Trigger

SSEL[0]

SSEL[1]

ADCB

Pre-
TriggerB 

System
Clock

TMR0

TMR1

SW

CMP0

CMP1

CMP2

PWM

EXT

Trigger0

Trigger1

Trigger2

Trigger3

Trigger4

Trigger5

Trigger6

Trigger7

Programmable Delay Block (PDB)