Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO
Модели
MC56F8006DEMO
Overview
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
5
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Parallel instruction set with unique DSP addressing modes
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Hardware DO and REP loops
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Three internal address buses
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Four internal data buses
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Instruction set supports DSP and controller functions
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Controller-style addressing modes and instructions for compact code
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Efficient C compiler and local variable support
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Software subroutine and interrupt stack with depth limited only by memory
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JTAG/enhanced on-chip emulation (EOnCE) for unobtrusive, processor speed–independent, real-time debugging
3.1.2
Operation Range
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1.8 V to 3.6 V operation (power supplies and I/O)
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From power-on-reset: approximately 1.9 V to 3.6 V
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Ambient temperature operating range:
— –40 °C to 125 °C
— –40 °C to 125 °C
3.1.3
Memory
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Dual Harvard architecture permits as many as three simultaneous accesses to program and data memory
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Flash security and protection that prevent unauthorized users from gaining access to the internal flash
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On-chip memory
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
— 16 KB of program flash for 56F8006 and 12 KB of program flash for 56F8002
— 2 KB of unified data/program RAM
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EEPROM emulation capability using flash
3.1.4
Interrupt Controller
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Five interrupt priority levels
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3
— Three user programmable priority levels for each interrupt source: Level 0, 1, 2
— Unmaskable level 3 interrupts include: illegal instruction, hardware stack overflow, misaligned data access, SWI3
instruction. Maskable level 3 interrupts include: EOnCE step counter, EOnCE breakpoint unit, EOnCE trace
buffer
buffer
— Lowest-priority software interrupt: level LP
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Allow nested interrupt that higher priority level interrupt request can interrupt lower priority interrupt subroutine
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The masking of interrupt priority level is managed by the 56800E core
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One programmable fast interrupt that can be assigned to any interrupt source
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Notification to system integration module (SIM) to restart clock out of wait and stop states
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Ability to relocate interrupt vector table
3.1.5
Peripheral Highlights
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One multi-function, six-output pulse width modulator (PWM) module
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation
— Up to 96 MHz PWM operating clock
— 15 bits of resolution
— Center-aligned and edge-aligned PWM signal mode
— Phase shifting PWM pulse generation