Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO
Модели
MC56F8006DEMO
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor
58
•
Tri-stated, when a bus or signal is placed in a high impedance state
•
Data Valid state, when a signal level has reached V
OL
or V
OH
•
Data Invalid state, when a signal level is in transition between V
OL
and V
OH
Figure 26. Signal States
8.13.1
Serial Peripheral Interface (SPI) Timing
Table 29. SPI Timing
1
Characteristic
Symbol
Min
Max
Unit
See Figure
Cycle time
Master
Slave
t
C
125
62.5
—
—
—
ns
ns
ns
Enable lead time
Master
Slave
t
ELD
—
31
—
—
—
ns
ns
ns
Enable lag time
Master
Slave
t
ELG
—
125
—
—
—
ns
ns
ns
Clock (SCK) high time
Master
Slave
t
CH
50
31
31
—
—
—
ns
ns
ns
Clock (SCK) low time
Master
Slave
t
CL
50
31
31
—
—
—
ns
ns
ns
Data set-up time required for inputs
Master
Slave
t
DS
20
0
—
—
—
ns
ns
ns
Data hold time required for inputs
Master
Slave
t
DH
0
2
2
—
—
—
ns
ns
ns
Access time (time to data active from high-impedance
state)
Slave
Slave
t
A
4.8
15
ns
Disable time (hold time to high-impedance state)
Slave
t
D
3.7
15.2
ns
Data Invalid State
Data1
Data3 Valid
Data2
Data3
Data1 Valid
Data Active
Data Active
Data2 Valid
Data
Three-stated
Three-stated