Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO

Freescale Semiconductor

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 lists major changes between versions of the MC56F8006 document.

 provides the 56F8006/56F8002’s reset and interrupt priority structure, including on-chip peripherals. The table is 

organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. As indicated, the priority of an 
interrupt can be assigned to different levels, allowing some control over interrupt priorities. All level 3 interrupts are serviced 
before level 2 and so on. For a selected priority level, the lowest vector number has the highest priority.

The location of the vector table is determined by the vector base address (VBA). Please see the MC56F8006 Peripheral 
Reference Manual for detail.

By default, the chip reset address and COP reset address correspond to vector 0 and 1 of the interrupt vector table. In these 
instances, the first two locations in the vector table must contain branch or JMP instructions. All other entries must contain JSR 
instructions.

Introduction 

Added part marking for devices covered by this document

,” 

Updated routing details for ANB24 and ANB25

Removed row about open drain mode (GPIO supports only push-pull mode)

Updated specifications for low-voltage detection threshold (high and low range) and 
low-voltage warning threshold

Updated all Supply Current Consumption specifications

 and 

Updated ROSC variation over temperature specifications (both ranges)

Removed I

2

C fast mode specifications and footnote about setup time if the TX FIFO 

is empty (fast mode and FIFO not supported)

Appendix 

Added note explaining ADC and GPIO naming conventions

For I2C_SMB_CSR, clarified that bits 7 and 6 are reserved

Throughout document.

Added information for 32-pin PSDIP device and devices with temperature range 
from –40

C to + 125 C.