Техническая Спецификация для Freescale Semiconductor MC56F8006 Demo board MC56F8006DEMO MC56F8006DEMO

Модели

MC56F8006DEMO

Overview

MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4

Freescale Semiconductor

3.3

Architecture Block Diagram

The 56F8006/56F8002’s architecture is shown in

illustrates how the 56800E system buses

communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core.

Figure 3

shows the peripherals and control blocks connected to the IPBus bridge.

Please see the system integration module

(SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other
peripherals.

Figure 2. 56800E Core Block Diagram

Data

DSP56800E Core

Arithmetic
Logic Unit

(ALU)

XAB2

PAB

PDB

CDBW

CDBR

XDB2

Program

Memory

Data/

IPBus

Interface

Bit-

Manipulation

Unit

M01

Address

XAB1

Generation

Unit

(AGU)

LA2

HWS0
HWS1

FIRA

OMR

FISR

LC2

Instruction

Decoder

Interrupt

Unit

Looping

Unit

Program Control Unit

ALU1

ALU2

MAC and ALU

Y1
Y0
X0

Enhanced

JTAG TAP

R2
R3
R4
R5

R0
R1

Multi-Bit Shifter

OnCE™

Program

RAM