Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
101
2.3.24
Port S Data Direction Register (DDRS)
Address 0x024A
Access: User read/write
1
1
Read: Anytime.
Write: Anytime.
Write: Anytime.
7
6
5
4
3
2
1
0
R
DDRS7
DDRS6
DDRS5
DDRS4
DDRS3
DDRS2
DDRS1
DDRS0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-22. Port S Data Direction Register (DDRS)
Table 2-19. DDRS Register Field Descriptions
Field
Description
7
DDRS
Port S data direction—
This register controls the data direction of pin 7.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, the IIC determines the pin direction, it will force as open-drain output
Else if PWM3 is routing to PS and PWM3 is enabled it will force as output.
This register controls the data direction of pin 7.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, the IIC determines the pin direction, it will force as open-drain output
Else if PWM3 is routing to PS and PWM3 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
6
DDRS
Port S data direction—
This register controls the data direction of pin 6.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM2 is routing to PS and PWM2 is enabled it will force as output.
This register controls the data direction of pin 6.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM2 is routing to PS and PWM2 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
5
DDRS
Port S data direction—
This register controls the data direction of pin 5.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM1 is routing to PS and PWM1 is enabled it will force as output.
This register controls the data direction of pin 5.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else if PWM1 is routing to PS and PWM1 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.
4
DDRS
Port S data direction—
This register controls the data direction of pin 4.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, it will force as open-drain output
Else if PWM0 is routing to PS and PWM0 is enabled it will force as output.
This register controls the data direction of pin 4.This register configures pin as either input or output.
If SPI is routing to PS and SPI is enabled, the SPI determines the pin direction
Else If IIC is routing to PS and IIC is enabled, it will force as open-drain output
Else if PWM0 is routing to PS and PWM0 is enabled it will force as output.
1 Associated pin is configured as output.
0 Associated pin is configured as input.
0 Associated pin is configured as input.