Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
108
Freescale Semiconductor
2.3.33
Port M Data Direction Register (DDRM)
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTM or PTIM registers, when changing the
DDRT register.
until the correct value is read on PTM or PTIM registers, when changing the
DDRT register.
Table 2-26. PTIM Register Field Descriptions
Field
Description
3-0
PTIM
Port M input data—
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
A read always returns the buffered input state of the associated pin. It can be used to detect overload or short circuit
conditions on output pins.
Address 0x0252
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
0
0
0
0
DDRM3
DDRM2
DDRM1
DDRM0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-30. Port M Data Direction Register (DDRM)
Table 2-27. DDRM Register Field Descriptions
Field
Description
3-2
DDRM
Port M data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding output compare channel is enabled, it will be forced as output.
Else if the corresponding PWM7-6 are enabled, the corresponding I/O state will be forced to output. In this case the
data direction bit will not change.
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding output compare channel is enabled, it will be forced as output.
Else if the corresponding PWM7-6 are enabled, the corresponding I/O state will be forced to output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input
1-0
DDRM
Port T data direction—
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding output compare channel is enabled, it will be forced as output.
Else if the corresponding PWM5-4 are enabled, the corresponding I/O state will be forced to output. In this case the
data direction bit will not change.
This bit determines whether the pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else If corresponding output compare channel is enabled, it will be forced as output.
Else if the corresponding PWM5-4 are enabled, the corresponding I/O state will be forced to output. In this case the
data direction bit will not change.
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input