Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
150
Freescale Semiconductor
2.3.96
Port V Routing Register (PTVRR)
This register configures the re-routing of TIM1 channels on alternative pins on Port M/V.
2.4
Functional Description
2.4.1
General
Each pin except BKGD can act as general purpose I/O. In addition each pin can act as an output or input
of a peripheral module.
of a peripheral module.
2.4.2
Registers
A set of configuration registers is common to all ports with exception of the ATD port (
). All
registers can be written at any time, however a specific configuration might not become active.
For example selecting a pull-up device: This device does not become active while the port is used as a
push-pull output.
push-pull output.
Address 0x029F
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
Write: Unimplemented
7
6
5
4
3
2
1
0
R
0
0
0
0
PTVRR3
PTVRR2
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
u = Unaffected by reset
Figure 2-93. Port V Routing Register (PTVRR)
Table 2-79. Port V Routing Register Field Descriptions
Field
Description
2
PTVRR
Port V Routing Register—
This register controls the routing of IOC1_2
This register controls the routing of IOC1_2
0 IOC1_2 routed to PV4
1 IOC1_2 routed to PM2
1 IOC1_2 routed to PM2
3
PTVRR
Port V Routing Register—
This register controls the routing of IOC1_3.
This register controls the routing of IOC1_3.
0 IOC1_3 routed to PV6
1 IOC1_3 routed to PM3
1 IOC1_3 routed to PM3