Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Interrupt (S12XINTV2)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
187
4.3.2.1
Interrupt Vector Base Register (IVBR)
Read: Anytime
Write: Anytime
4.3.2.2
XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Read: Anytime
Write: Anytime
Address: 0x0121
7
6
5
4
3
2
1
0
R
IVB_ADDR[7:0]
W
Reset
1
1
1
1
1
1
1
1
Figure 4-3. Interrupt Vector Base Register (IVBR)
Table 4-4. IVBR Field Descriptions
Field
Description
7–0
IVB_ADDR[7:0]
Interrupt Vector Base Address Bits — These bits represent the upper byte of all vector addresses. Out of
reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
reset these bits are set to 0xFF (i.e., vectors are located at 0xFF10–0xFFFE) to ensure compatibility to
previous S12 microcontrollers.
Note: A system reset will initialize the interrupt vector base register with “0xFF” before it is used to determine
the reset vector address. Therefore, changing the IVBR has no effect on the location of the three reset
vectors (0xFFFA–0xFFFE).
vectors (0xFFFA–0xFFFE).
Note: If the BDM is active (i.e., the CPU is in the process of executing BDM firmware code), the contents of
IVBR are ignored and the upper byte of the vector address is fixed as “0xFF”.
Address: 0x0126
7
6
5
4
3
2
1
0
R
0
0
0
0
0
XILVL[2:0]
W
Reset
0
0
0
0
0
0
0
1
= Unimplemented or Reserved
Figure 4-4. XGATE Interrupt Priority Configuration Register (INT_XGPRIO)
Table 4-5. INT_XGPRIO Field Descriptions
Field
Description
2–0
XILVL[2:0]
XGATE Interrupt Priority Level — The XILVL[2:0] bits configure the shared interrupt level of the XGATE
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
interrupts coming from the XGATE module. Out of reset the priority is set to the lowest active level (“1”).
Note: If the XGATE module is not available on the device, write accesses to this register are ignored and read
accesses to this register will return all 0.