Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Freescale Semiconductor

261

This specification describes the function of the Clocks and Reset Generator (S12XECRG).

The main features of this block are:

•

Phase Locked Loop (IPLL) frequency multiplier with internal filter

— Reference divider

— Post divider

— Configurable internal filter (no external pin)

— Optional frequency modulation for defined jitter and reduced emission

— Automatic frequency lock detector

— Interrupt request on entry or exit from locked condition

— Self Clock Mode in absence of reference clock

•

System Clock Generator

— Clock Quality Check

— User selectable fast wake-up from Stop in Self-Clock Mode for power saving and immediate

program execution

— Clock switch for either Oscillator or PLL based system clocks

•

Computer Operating Properly (COP) watchdog timer with time-out clear window.

•

System Reset generation from the following possible sources:

— Power on reset

— Low voltage reset

V02.00

18 Sep. 2009

Initial release derived from S12XECRG V01.04 plus modifications for LCD
clock output.

V02.01

19 Sep. 2012

Added footnote concerning maximum clock frequencies to table
Removed redundant examples from table
Replaced reference to MMC documentation in Reset section