Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Модели

DEMO9S12XHY256

Freescale’s Scalable Controller Area Network (S12MSCANV3)

MC9S12XHY-Family Reference Manual Rev. 1.04

Freescale Semiconductor

373

•

The transmission buffer with the lowest local priority field wins the prioritization.

In cases of more than one buffer having the same lowest priority, the message buffer with the lower index
number wins.

11.3.3.5

Time Stamp Register (TSRH–TSRL)

If the TIME bit is enabled, the MSCAN will write a time stamp to the respective registers in the active
transmit or receive buffer right after the EOF of a valid message on the CAN bus (see

Section 11.3.2.1,

“MSCAN Control Register 0 (CANCTL0)

”). In case of a transmission, the CPU can only read the time

stamp after the respective transmit buffer has been flagged empty.

The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.

Module Base + 0x00XD

Access: User read/write

(1)

1. Read: Anytime when TXEx flag is set (see

Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)

”) and the

corresponding transmit buffer is selected in CANTBSEL (see

Section 11.3.2.11, “MSCAN Transmit Buffer Selection Register

(CANTBSEL)

”)

Write: Anytime when TXEx flag is set (see

Section 11.3.2.7, “MSCAN Transmitter Flag Register (CANTFLG)