Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
421
Chapter 13
Pulse-Width Modulator (S12PWM8B8CV1)
Pulse-Width Modulator (S12PWM8B8CV1)
Table 13-1. Revision History
13.1
Introduction
The PWM definition is based on the HC12 PWM definitions. It contains the basic features from the HC11
with some of the enhancements incorporated on the HC12: center aligned output mode and four available
clock sources.The PWM module has eight channels with independent control of left and center aligned
outputs on each channel.
with some of the enhancements incorporated on the HC12: center aligned output mode and four available
clock sources.The PWM module has eight channels with independent control of left and center aligned
outputs on each channel.
Each of the eight channels has a programmable period and duty cycle as well as a dedicated counter. A
flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each
of the modulators can create independent continuous waveforms with software-selectable duty rates from
0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.
flexible clock select scheme allows a total of four different clock sources to be used with the counters. Each
of the modulators can create independent continuous waveforms with software-selectable duty rates from
0% to 100%. The PWM outputs can be programmed as left aligned outputs or center aligned outputs.
13.1.1
Features
The PWM block includes these distinctive features:
•
Eight independent PWM channels with programmable period and duty cycle
•
Dedicated counter for each PWM channel
•
Programmable PWM enable/disable for each channel
•
Software selection of PWM duty pulse polarity for each channel
•
Period and duty cycle are double buffered. Change takes effect when the end of the effective period
is reached (PWM counter reaches zero) or when the channel is disabled.
is reached (PWM counter reaches zero) or when the channel is disabled.
•
Programmable center or left aligned outputs on individual channels
•
Eight 8-bit channel or four 16-bit channel PWM resolution
•
Four clock sources (A, B, SA, and SB) provide for a wide range of frequencies
•
Programmable clock select logic
•
Emergency shutdown
13.1.2
Modes of Operation
There is a software programmable option for low power consumption in wait mode that disables the input
clock to the prescaler.
clock to the prescaler.
1.1
28 Sepr 2012
1.4.2.6
deleted the blank in the doc