Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Serial Peripheral Interface (S12SPIV5)
MC9S12XHY-Family Reference Manual, Rev. 1.04
500
Freescale Semiconductor
15.3.2.4
SPI Status Register (SPISR)
Read: Anytime
Write: Has no effect
1
1
0
1
1
0
896
27.90 kbit/s
1
1
0
1
1
1
1792
13.95 kbit/s
1
1
1
0
0
0
16
1.5625 Mbit/s
1
1
1
0
0
1
32
781.25 kbit/s
1
1
1
0
1
0
64
390.63 kbit/s
1
1
1
0
1
1
128
195.31 kbit/s
1
1
1
1
0
0
256
97.66 kbit/s
1
1
1
1
0
1
512
48.83 kbit/s
1
1
1
1
1
0
1024
24.41 kbit/s
1
1
1
1
1
1
2048
12.21 kbit/s
Module Base +0x0003
7
6
5
4
3
2
1
0
R
SPIF
0
SPTEF
MODF
0
0
0
0
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 15-6. SPI Status Register (SPISR)
Table 15-7. SPISR Field Descriptions
Field
Description
7
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to
information about clearing SPIF Flag, please refer to
0 Transfer not yet complete.
1 New data copied to SPIDR.
1 New data copied to SPIDR.
5
SPTEF
SPI Transmit Empty Interrupt Flag — If set, this bit indicates that the transmit data register is empty. For
information about clearing this bit and placing data into the transmit data register, please refer to
information about clearing this bit and placing data into the transmit data register, please refer to
.
0 SPI data register not empty.
1 SPI data register empty.
1 SPI data register empty.
4
MODF
Mode Fault Flag — This bit is set if the SS input becomes low while the SPI is configured as a master and mode
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
fault detection is enabled, MODFEN bit of SPICR2 register is set. Refer to MODFEN bit description in
. The flag is cleared automatically by a read of the SPI status
register (with MODF set) followed by a write to the SPI control register 1.
0 Mode fault has not occurred.
1 Mode fault has occurred.
0 Mode fault has not occurred.
1 Mode fault has occurred.
Table 15-6. Example SPI Baud Rate Selection (25 MHz Bus Clock) (Sheet 3 of 3)
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Baud Rate
Divisor
Baud Rate