Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Serial Peripheral Interface (S12SPIV5)
MC9S12XHY-Family Reference Manual Rev. 1.04
Freescale Semiconductor
509
Figure 15-13. SPI Clock Format 0 (CPHA = 0), with 16-Bit Transfer Width selected (XFRW = 1)
In slave mode, if the SS line is not deasserted between the successive transmissions then the content of the
SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted
for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the
SPI data register is transmitted.
SPI data register is not transmitted; instead the last received data is transmitted. If the SS line is deasserted
for at least minimum idle time (half SCK cycle) between successive transmissions, then the content of the
SPI data register is transmitted.
In master mode, with slave select output enabled the SS line is always deasserted and reasserted between
successive transfers for at least minimum idle time.
successive transfers for at least minimum idle time.
15.4.3.3
CPHA = 1 Transfer Format
Some peripherals require the first SCK edge before the first data bit becomes available at the data out pin,
the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the n
the second edge clocks data into the system. In this format, the first SCK edge is issued by setting the
CPHA bit at the beginning of the n
5
-cycle transfer operation.
The first edge of SCK occurs immediately after the half SCK clock cycle synchronization delay. This first
edge commands the slave to transfer its first data bit to the serial data input pin of the master.
edge commands the slave to transfer its first data bit to the serial data input pin of the master.
A half SCK cycle later, the second edge appears on the SCK pin. This is the latching edge for both the
master and slave.
master and slave.
5. n depends on the selected transfer width, please refer to
t
L
Begin
End
SCK (CPOL = 0)
SAMPLE I
CHANGE O
SEL SS (O)
Transfer
SCK (CPOL = 1)
MSB first (LSBFE = 0)
LSB first (LSBFE = 1)
MSB
LSB
LSB
MSB
Bit 13
Bit 2
Bit 14
Bit 1
Bit 12
Bit 3
Bit 11
Bit 4
Bit 5
CHANGE O
SEL SS (I)
MOSI pin
MISO pin
Master only
MOSI/MISO
t
T
If ne
xt tr
ansf
er begins here
for t
T
, t
l
, t
L
Minimum 1/2 SCK
t
I
t
L
t
L
= Minimum leading time before the first SCK edge
t
T
= Minimum trailing time after the last SCK edge
t
I
= Minimum idling time between transfers (minimum SS high time)
t
L
, t
T
, and t
I
are guaranteed for the master mode and required for the slave mode.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCK Edge Number
End of Idle State
Begin of Idle State
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
Bit 10 Bit 9 Bit 8 Bit 7 Bit 6
Bit 4 Bit 3 Bit 2 Bit 1
Bit 6
Bit 5
Bit 7 Bit 8 Bit 9 Bit 10Bit 11Bit 12Bit 13Bit 14