Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256
Модели
DEMO9S12XHY256
Liquid Crystal Display (LCD40F4BV2) Block Description
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
555
17.4
Functional Description
This section provides a complete functional description of the LCD40F4BV2 block, detailing the
operation of the design from the end user perspective in a number of subsections.
operation of the design from the end user perspective in a number of subsections.
17.4.1
LCD Driver Description
17.4.1.1
Frontplane, Backplane, and LCD System During Reset
During a reset the following conditions exist:
•
The LCD40F4BV2 system is configured in the default mode, 1/4 duty and 1/3 bias, that means all
backplanes are used.
backplanes are used.
•
All frontplane enable bits, FP[39:0]EN are cleared and the ON/OFF control for the display, the
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
LCDEN bit is cleared, thereby forcing all frontplane and backplane driver outputs to the high
impedance state. The MCU pin state during reset is defined by the port integration module (PIM).
17.4.1.2
LCD Clock and Frame Frequency
The frequency of the source clock (IRCCLK) and divider determine the LCD clock frequency. The divider
is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0).
is set by the LCD clock prescaler bits, LCLK[2:0], in the LCD control register 0 (LCDCR0).
shows the LCD clock and frame frequency for some multiplexed mode at IRCCLK = 16 MHz, 8 MHz, 4
MHz, 2 MHz, 1 MHz, and 0.5 MHz.
MHz, 2 MHz, 1 MHz, and 0.5 MHz.
Table 17-7. LCD RAM Field Descriptions
Field
Description
39:0
3:0
FP[39:0]
BP[3:0]
LCD Segment ON — The FP[39:0]BP[3:0] bit displays (turns on) the LCD segment connected between FP[39:0]
and BP[3:0].
0 LCD segment OFF
1 LCD segment ON
and BP[3:0].
0 LCD segment OFF
1 LCD segment ON
Table 17-8. LCD Clock and Frame Frequency
Source clock
Frequency in
Frequency in
MHz
LCD Clock Prescaler
Divider
LCD Clock
Frequency [Hz]
Frame Frequency [Hz]
LCLK2
LCLK1
LCLK0
1/1 Duty
1/2 Duty
1/3 Duty
1/4 Duty
IRCCLK = 0.5
0
0
0
0
0
0
0
1
1
1024
2048
2048
488
244
244
488
244
244
244
122
122
163
81
122
61
IRCCLK = 1.0
0
0
0
0
1
1
1
0
0
2048
4096
4096
488
244
244
488
244
244
244
122
122
163
81
122
61
IRCCLK = 2.0
0
0
0
1
1
1
0
1
1
4096
8192
8192
488
244
244
488
244
244
244
122
122
163
81
122
61
IRCCLK = 4.0
0
1
1
1
0
0
1
0
0
8192
16384
488
244
244
488
244
244
244
122
122
163
81
122
61
IRCCLK = 8.0
1
1
1
0
0
0
0
1
1
16384
32768
32768
488
244
244
488
244
244
244
122
122
163
81
122
61