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The Flash module can generate an interrupt when a Flash command operation has completed or when a
Flash command operation has detected an ECC fault.

Vector addresses and their relative interrupt priority are determined at the
MCU level.

The Flash module uses the CCIF flag in combination with the CCIE interrupt enable bit to generate the
Flash command interrupt request. The Flash module uses the DFDIF and SFDIF flags in combination with
the DFDIE and SFDIE interrupt enable bits to generate the Flash error interrupt request. For a detailed
description of the register bits involved, refer to

”,

”, and

The logic used for generating the Flash module interrupts is shown in

FSTAT

ACCERR

Set if CCOBIX[2:0] != 001 at command launch

Set if command not available in current mode (see

)

Set if an invalid global address [22:0] is supplied

Set if a misaligned word address is supplied (global address [0] != 0)

FPVIOL

Set if the selected area of the D-Flash memory is protected

MGSTAT1

Set if any errors have been encountered during the verify operation

MGSTAT0

Set if any non-correctable errors have been encountered during the verify
operation

Flash Command Complete

CCIF

(FSTAT register)

CCIE

(FCNFG register)

I Bit

ECC Double Bit Fault on Flash Read

DFDIF

(FERSTAT register)

DFDIE

(FERCNFG register)

I Bit

ECC Single Bit Fault on Flash Read

SFDIF

(FERSTAT register)

SFDIE

(FERCNFG register)

I Bit