Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Модели

DEMO9S12XHY256

Motor Controller (MC10B8CV1)

MC9S12XHY-Family Reference Manual, Rev. 1.04

676

Freescale Semiconductor

20.3.2.4

Motor Controller Channel Control Registers

Each PWM channel has one associated control register to control output delay, PWM alignment, and
output mode. The registers are named MCCC0... MCCC7. In the following, MCCC0 is described as a
reference for all eight registers.

Offset Module Base + 0x0010 . . . 0x0017

MCOM1

MCOM0

MCAM1

MCAM0

CD1

CD0

Reset

= Unimplemented or Reserved

Figure 20-7. Motor Controller Control Register Channel 0–7 (MCCC0–MCCC7)

Table 20-6. MCCC0–MCCC7 Field Descriptions

Field

Description

7:6

MCOM[1:0]

Output Mode — MCOM1, MCOM0 control the PWM channel’s output mode. See

Table 20-7

5:4

MCAM[1:0]

PWM Channel Alignment Mode — MCAM1, MCAM0 control the PWM channel’s PWM alignment mode and

operation. See

Table 20-8

MCAM[1:0] and MCOM[1:0] are double buffered. The values used for the generation of the output waveform
will be copied to the working registers either at once (if all PWM channels are disabled or MCPER is set to 0)
or if a timer counter overflow occurs. Reads of the register return the most recent written value, which are not
necessarily the currently active values.

1:0

CD[1:0]

PWM Channel Delay — Each PWM channel can be individually delayed by a programmable number of PWM

timer counter clocks. The delay will be n/f

. See

Table 20-9

Table 20-7. Output Mode

MCOM[1:0]

Output Mode

Half H-bridge mode, PWM on MnCxM, MnCxP is released

Half H-bridge mode, PWM on MnCxP, MnCxM is released

Full H-bridge mode

Dual full H-bridge mode

Table 20-8. PWM Alignment Mode

MCAM[1:0]

PWM Alignment Mode

Channel disabled

Left aligned

Right aligned

Center aligned