Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

Freescale Semiconductor

1225

The time base for all NVM program or erase operations is derived from the bus clock using the FCLKDIV
register. The frequency of this derived clock must be set within the limits specified as f

NVMOP

. The NVM

module does not have any means to monitor the frequency and will not prevent program or erase operation
at frequencies above or below the specified minimum. When attempting to program or erase the NVM
module at a lower frequency, a full program or erase transition is not assured.

The following sections provide equations which can be used to determine the time required to execute
specific flash commands. All timing parameters are a function of the bus clock frequency, f

NVMBUS

. All

program and erase times are also a function of the NVM operating frequency, f

NVMOP

. A summary of key

timing parameters can be found in

.

8

C

Output Voltage
unbuffered range A or B (load >= 50M

Ω)

V

out

full DAC Range A or B

V

9

P

Output Voltage (DRIVE bit = 0)

1

buffered range A (load >= 100K

Ω to VSSA)

buffered range A (load >= 100K

Ω to VDDA)

buffered range B (load >= 100K

Ω to VSSA)

buffered range B (load >= 100K

Ω to VDDA)

V

out

0

0.15

-
-

VDDA-0.15

VDDA

V

full DAC Range B

10

P

Output Voltage (DRIVE bit = 1)

2

buffered range B with 6.4K

Ω load into resistor

divider of 800

Ω /6.56KΩ between VDDA and

VSSA.
(equivalent load is >= 65K

Ω to VSSA) or

(equivalent load is >= 7.5K

Ω to VDDA)

V

out

full DAC Range B

V

11

D

Buffer Output Capacitive load

C

load

0

-

100

pF

12

P

Buffer Output Offset

V

offset

-30

-

+30

mV

13

P

Settling time

t

delay

-

3

5

µs

14

D

Reverence voltage high

V

refh

VDDA-0.1V

VDDA

VDDA+0.1V

V

1

DRIVE bit = 1 is not recommended in this case.

2

DRIVE bit = 0 is not allowed with this high load.

Characteristics noted under conditions 3.13V <= VDDA <= 5.5V>, -40˚C < Tj < 150˚C >, VRH=VDDA, VRL=VSSA
unless otherwise noted. Typical values noted reflect the approximate parameter mean at T

A

 = 25˚C under nominal

conditions unless otherwise noted.