Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Electrical Characteristics
MC9S12G Family Reference Manual,
Rev.1.23
1230
Freescale Semiconductor
FTMRG128K1, FTMRG96K1:
FTMRG64K1, FTMRG48K1:
FTMRG32K1, FTMRG16K1:
A.7.1.11
Verify Backdoor Access Key (FCMD=0x0C)
The maximum verify backdoor access key time is given by:
A.7.1.12
Set User Margin Level (FCMD=0x0D)
The maximum set user margin level time is given by:
A.7.1.13
Set Field Margin Level (FCMD=0x0E)
The maximum set field margin level time is given by:
A.7.1.14
Erase Verify EEPROM Section (FCMD=0x10)
The time required to Erase Verify EEPROM for a given number of words N
W
is given by:
t
uns
100070
1
f
NVMOP
------------------
33500
1
f
NVMBUS
---------------------
⋅
+
⋅
≈
t
uns
100070
1
f
NVMOP
------------------
18300
1
f
NVMBUS
---------------------
⋅
+
⋅
≈
t
uns
100070
1
f
NVMOP
------------------
9600
1
f
NVMBUS
---------------------
⋅
+
⋅
≈
t
520
1
f
NVMBUS
---------------------
⋅
=
t
500
1
f
NVMBUS
---------------------
⋅
=
t
510
1
f
NVMBUS
---------------------
⋅
=
t
dcheck
520
N
W
+
(
)
1
f
NVMBUS
---------------------
⋅
≈