Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Detailed Register Address Map
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
1249
Appendix B
Detailed Register Address Map
Detailed Register Address Map
Revision History
B.1
Detailed Register Map
The following tables show the detailed register map of the MC9S12G-Family.
NOTE
This is a summary of all register bits implemented on MC9S12G devices.
Each member of the MC9S12G-Family implements the subset of registers,
which is associated with its feature set (see
Each member of the MC9S12G-Family implements the subset of registers,
which is associated with its feature set (see
Version
Number
Revision
Date
Description of Changes
Rev 0.05
30-Aug-2010
• Updated ADCCTL2 register in
.
• Updated CPMUOSC register in
.
Rev 0.06
18-Oct-2010
• Updated ADC registers in
Rev 0.07
9-Nov-2010
• Updated CPMU registers in
”
.
Rev 0.08
4-Dec-2010
• Updated PIM registers in
.
Rev 0.09
24-Apr-2012
• Typos and formatting
0x0000–0x0009 Port Integration Module (PIM) Map 1 of 6
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x0000
PORTA
R
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA 0
W
0x0001
PORTB
R
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
W
0x0002
DDRA
R
DDRA7
DDRA6
DDRA5
DDRA4
DDRA3
DDRA2
DDRA1
DDRA0
W
0x0003
DDRB
R
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W
0x0004
PORTC
R
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
W
0x0005
PORTD
R
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
W
0x0006
DDRC
R
DDRC7
DDRC6
DDRC5
DDRC4
DDRC3
DDRC2
DDRC1
DDRC0
W
0x0007
DDRD
R
DDRD7
DDRD6
DDRD5
DDRD4
DDRD3
DDRD2
DDRD1
DDRD0
W
0x0008
PORTE
R
0
0
0
0
0
0
PE1
PE0
W
0x0009
DDRE
R
0
0
0
0
0
0
DDRE1
DDRE0
W