Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT

Freescale Semiconductor

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The operating mode out of reset is determined by the state of the MODC signal during reset (see

). The MODC bit in the MODE register shows the current operating mode and provides limited

mode switching during operation. The state of the MODC signal is latched into this bit on the rising edge
of RESET.

This mode is intended for normal device operation. The opcode from the on-chip memory is being
executed after reset (requires the reset vector to be programmed correctly). The processor program is
executed from internal memory.

This mode is used for debugging single-chip operation, boot-strapping, or security related operations. The
background debug module BDM is active in this mode. The CPU executes a monitor program located in
an on-chip ROM. BDM firmware waits for additional serial commands through the BKGD pin.

The MC9S12G has two static low-power modes Pseudo Stop and Stop Mode. For a detailed description
refer to S12CPMU section.

The MCU security mechanism prevents unauthorized access to the Flash memory. Refer to

,

, and

.

Consult the S12 CPU manual and the S12SINT section for information on exception processing.

Table 1-34. lists all Reset sources and the vector locations. Resets are explained in detail in the

.

Normal single chip

1

Special single chip

0