Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
173
2.3.5
Pins PD7-0
2.3.6
Pins PE1-0
2.3.7
Pins PT7-0
Table 2-9. Port
Pins PD7-0
PD7-PD0
• These pins feature general-purpose I/O functionality only.
Table 2-10. Port
Pins PE1-0
PE1
• If the CPMU OSC function is active this pin is used as XTAL signal and the pulldown device is disabled.
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0
• 20 TSSOP: The SCI0 TXD signal is mapped to this pin when used with the SCI function. If the SCI0
TXD signal is enabled and routed here the I/O state will depend on the SCI0 configuration.
• 20 TSSOP: The TIM channel 3 signal is mapped to this pin when used with the timer function. The TIM
forces the I/O state to be an output for a timer port associated with an enabled output compare.
• 20 TSSOP: The PWM channel 1 signal is mapped to this pin when used with the PWM function. The
enabled PWM channel forces the I/O state to be an output.
• 20 TSSOP: The ADC ETRIG1 signal is mapped to this pin when used with the ADC function. The
enabled external trigger function has no effect on the I/O state. Refer to
• Signal priority:
20 TSSOP: XTAL > TXD0 > IOC3 > PWM1 > GPO
Others: XTAL > GPO
Others: XTAL > GPO
PE0
• If the CPMU OSC function is active this pin is used as EXTAL signal and the pulldown device is
disabled.
• 20 TSSOP: The SCI0 RXD signal is mapped to this pin when used with the SCI function. If the SCI0
RXD signal is enabled and routed here the I/O state will be forced to input.
• 20 TSSOP: The TIM channel 2 signal is mapped to this pin when used with the timer function. The TIM
forces the I/O state to be an output for a timer port associated with an enabled output compare.
• 20 TSSOP: The PWM channel 0 signal is mapped to this pin when used with the PWM function. The
enabled PWM channel forces the I/O state to be an output.
• 20 TSSOP: The ADC ETRIG0 signal is mapped to this pin when used with the ADC function. The
enabled external trigger function has no effect on the I/O state. Refer to
• Signal priority:
20 TSSOP: EXTAL > RXD0 > IOC2 > PWM0 > GPO
Others: EXTAL > GPO
Others: EXTAL > GPO
Table 2-11. Port
Pins PT7-0
PT7-PT6
• 64/100 LQFP: The TIM channels 7 and 6 signal are mapped to these pins when used with the timer
function. The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare.
compare.
• Signal priority:
64/100 LQFP: IOC7-6 > GPO
PT5
• 48/64/100 LQFP: The TIM channel 5 signal is mapped to this pin when used with the timer function.
The TIM forces the I/O state to be an output for a timer port associated with an enabled output
compare. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can
still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires
the timer input capture function to be enabled.
compare. If the ACMP timer link is enabled this pin is disconnected from the timer input so that it can
still be used as general-purpose I/O or as timer output. The use case for the ACMP timer link requires
the timer input capture function to be enabled.
• Signal priority:
48/64/100 LQFP: IOC5 > GPO